1. 31 Jul, 2015 5 commits
    • Zoe Liu's avatar
      Refactor mips/dspr2 on convolution. · 7cfdc003
      Zoe Liu authored
      Change-Id: If59a39d5a92c261537342726f94bb7f7f26dfff3
      7cfdc003
    • Zoe Liu's avatar
      Code refactor on InterpKernel · 7186a2dd
      Zoe Liu authored
      It in essence refactors the code for both the interpolation
      filtering and the convolution. This change includes the moving
      of all the files as well as the changing of the code from vp9_
      prefix to vpx_ prefix accordingly, for underneath architectures:
      (1) x86;
      (2) arm/neon; and
      (3) mips/msa.
      The work on mips/drsp2 will be done in a separate change list.
      
      Change-Id: Ic3ce7fb7f81210db7628b373c73553db68793c46
      7186a2dd
    • Parag Salasakar's avatar
      mips msa vp8 block subtract optimization · 0e3f494b
      Parag Salasakar authored
      average improvement ~2x-3x
      
      Change-Id: I30abf4c92cddcc9e87b7a40d4106076e1ec701c2
      0e3f494b
    • Parag Salasakar's avatar
      e3ee8c29
    • Yunqing Wang's avatar
      Remove tx cache and speed up tx size selection · 3b2e73b9
      Yunqing Wang authored
      1. The RD scores obtained during the tx size selection were stored in the
      tx cache, and used to help make the tx decision for the following frames.
      This wasn't used anymore in VP9 encoder. Recovered the related decision
      making code from 1.5+ years ago, and borg tests didn't show any quality
      gain. This patch removed it to lower the complexity.
      
      2. An optimization was done after the above refactoring. If the tx_mode
      is not TX_MODE_SELECT, we only need to test the chosen tx size instead
      of all posible tx sizes. This gave a 1.5% average speed gain at speed 2,
      and a 1% average speed gain at speed 3.
      
      Change-Id: Id8cd650e066a8cef33829d8c15388a8138adc78c
      3b2e73b9
  2. 30 Jul, 2015 12 commits
  3. 29 Jul, 2015 11 commits
  4. 28 Jul, 2015 12 commits