Android.mk should depend on vpx_dsp_rtcd.h

Change-Id: Ib614af195a9574fd849c28b695f9f4b3b2bd125c

Use memcpy instead of casting.

Change-Id: Ieca725cc628883985bde23c7d742af8781c5dbb5

this macro was used inconsistently and only differs in behavior from
DECLARE_ALIGNED when an alignment attribute is unavailable. this macro
is used with calls to assembly, while generic c-code doesn't rely on it,
so in a c-only build without an alignment attribute the code will
function as expected.

Change-Id: Ie9d06d4028c0de17c63b3a27e6c1b0491cc4ea79

average improvement ~4x-6x

Change-Id: Idaba7e49fbd7f388caee0d73773ccf6e4807ef17

vp9_dc_left_predictor_16x16
vp9_dc_top_predictor_32x32
vp9_dc_left_predictor_32x32
vp9_dc_128_predictor_32x32

Change-Id: Ib9861deefd01c3527235b92ff6b3d571ef6b4bc6

Using EIGHTTAP and EIGHTTAP_SMOOTH seem sufficient.
Hard to see any visual gain from allowing EIGHTTAP_SHARP, and it is
rarely selected.

PSNR/SSIM metrics go up by ~0.18/0.14%.

Change-Id: I96fa0d98f9321b913e3ebcd464d4ff3c63018791

Create a new component, vpx_dsp, for code that can be shared
between codecs. Move the SAD code into the component.

This reduces the size of vpxenc/dec by 36k on x86_64 builds.

Change-Id: I73f837ddaecac6b350bf757af0cfe19c4ab9327a

Change-Id: Id0f224ac4667dd173363b0f05711678448291d4e

times of border extension.

Change-Id: I8e5bd590cc696ee71cfe1f4cc66c12fb24aaf44e

Added the intra mode early termination in order to
speed up the mode search in non-rd case since we
started to include more intra modes in the search
list. Borg tests(rtc set) showed a 0.048% PSNR gain
and 0.061 SSIM gain. No speed change.

Change-Id: I6f255fe534dc50b736e6a66a726ad458eb9b4443

Change-Id: I5a796425ce5706824a2fc17c6f24f983c5b9e43b

widen the loads and stores to 128-bit.

this was added, but not enabled in:
493a8579 Add some sse2 code for intra prediction.

Change-Id: I277d7db608a7db7d75cc0bde86f48fa66ad487e4

average improvement ~4x-6x

Change-Id: I55e95b7f2ba403dff11813958dc7c73a900dd022

For non-rd mode (speed >=5): use mask based on prediction block size, and
(for non-screen content mode) allow for checking horiz and vert intra modes
for blocks sizes < 16x16.

Avg psnr/ssim metrics go up by about ~0.2%.

Only allowing H/V intra on block sizes below 16x16 for now, to keep
encoding time increase very small, and also when allowing H/V on 16x16 blocks,
metrics went down on a few clips which need to be further examined.

Change-Id: I8ae0bc8cb2a964f9709612c76c5661acaab1381e

+ fix some whitespace

Change-Id: Id61b739282014288a7e5d3c17a9d6448d9d4cda2

Should be using xd->above_mi and xd->left_mi.

Change-Id: Ifab83512db5491a955a3ed44a2d6e3b25b5ae5a5

Impose a limit on the rd auto partition search based on
the image format. Smaller formats require that the search
includes includes a smaller minimum block size.

This change is intended to mitigate the visual impact of
ringing in some problem clips, for smaller image formats.

Change-Id: Ie039e5f599ee079bbef5d272f3e40e2e27d8f97b

Remove one of the auto partition size cases.
This case can behaves badly in some types of animated content
and was only used for the rd encode path. A subsequent patch
will add additional checks to help further improve visual quality.

Change-Id: I0ebd8da3d45ab8501afa45d7959ced8c2d60ee4e

Previously limit on max interval  set to 0.5 seconds.
Though this helped some low frame rate material it
appears to be a bit too aggressive for some 24 and 25 fps
content. This patch relaxes the limit to 0.75 seconds.

The patch also adds a new minimum interval variable
to replace the current hard wired value. This allows us
to impose a limit on the maximum number of primary
arfs per second for high frame rate (e.g. 50 & 60fps)
content. This is to address concerns regarding playback
performance on some platforms if there is a high base
frame rate and very frequent arfs.

Change-Id: I373e8b6b2a8ef522eced6c6d2cceb234ff763fcf

offsetting by a variable stride prevents instruction reordering,
resulting in poor assembly

Change-Id: Id62d6b3299cdd23f8c44f97b630abf4fea241446

offsetting by a variable stride prevents instruction reordering,
resulting in poor assembly.
additionally reroll 16x16/32x32 loops to reduce register spill with this
new format

Change-Id: I0635b8ba21ecdb88116e927dbdab53acdf256e11

Change-Id: I16c0a62e52dab62837c547345df31e7518620ed4