This reduces the multiplier width of daala_ec from 16x15->31 to
8x15->23, which reduces hardware latency by an estimated 20% (and
area for this module by an estimated 40%).

These are the smallest logical changes required to achieve this,
but the approach will be optimized significantly in subsequent
commits.

When enabled:

ec_smallmul1c_base@2017-03-08T00:49:01.830Z ->
 ec_smallmul1c@2017-03-08T00:49:45.091Z

  PSNR | PSNR Cb | PSNR Cr | PSNR HVS |   SSIM | MS SSIM | CIEDE 2000
0.0203 |  0.0203 |  0.0204 |   0.0203 | 0.0203 |  0.0203 |     0.0202

Change-Id: Idbbd3743e9189146cb519d5b984bdabd69e3f4c0