diff --git a/vp9/common/arm/neon/vp9_convolve8_avg_neon.asm b/vp9/common/arm/neon/vp9_convolve8_avg_neon.asm
index 536841114efb216ba5b6c81be31b751ff4b2dfe8..110a56cddc9d9462e9f84fd01db874e7bc12638b 100644
--- a/vp9/common/arm/neon/vp9_convolve8_avg_neon.asm
+++ b/vp9/common/arm/neon/vp9_convolve8_avg_neon.asm
@@ -128,8 +128,8 @@ loop_horiz
     vqrshrun.s32    d5, q15, #7
 
     ; saturate
-    vqshrn.u16      d2, q1, #0
-    vqshrn.u16      d3, q2, #0
+    vqmovn.u16      d2, q1
+    vqmovn.u16      d3, q2
 
     ; transpose
     vtrn.16         d2, d3
@@ -137,10 +137,7 @@ loop_horiz
     vtrn.8          d2, d3
     
     ; average the new value and the dst value
-    vaddl.u8        q8, d2, d6
-    vaddl.u8        q9, d3, d7
-    vqrshrn.u16     d2, q8, #1
-    vqrshrn.u16     d3, q9, #1
+    vrhadd.u8       q1, q1, q3
 
     vst1.u32        {d2[0]}, [r2], r3
     vst1.u32        {d3[0]}, [r2], r3
@@ -234,14 +231,11 @@ loop_vert
     vqrshrun.s32    d5, q15, #7
 
     ; saturate
-    vqshrn.u16      d2, q1, #0
-    vqshrn.u16      d3, q2, #0
+    vqmovn.u16      d2, q1
+    vqmovn.u16      d3, q2
 
     ; average the new value and the dst value
-    vaddl.u8        q8, d2, d6
-    vaddl.u8        q9, d3, d7
-    vqrshrn.u16     d2, q8, #1
-    vqrshrn.u16     d3, q9, #1
+    vrhadd.u8       q1, q1, q3
 
     vst1.u32        {d2[0]}, [r2], r3
     vst1.u32        {d2[1]}, [r2], r3
diff --git a/vp9/common/arm/neon/vp9_convolve8_neon.asm b/vp9/common/arm/neon/vp9_convolve8_neon.asm
index 9146243829a8ffbdd2c906be2b3b62150467dc93..845e4a8660bdd2224213b02e14c709b0d2078320 100644
--- a/vp9/common/arm/neon/vp9_convolve8_neon.asm
+++ b/vp9/common/arm/neon/vp9_convolve8_neon.asm
@@ -120,8 +120,8 @@ loop_horiz
     vqrshrun.s32    d5, q15, #7
 
     ; saturate
-    vqshrn.u16      d2, q1, #0
-    vqshrn.u16      d3, q2, #0
+    vqmovn.u16      d2, q1
+    vqmovn.u16      d3, q2
 
     ; transpose
     vtrn.16         d2, d3
@@ -213,8 +213,8 @@ loop_vert
     vqrshrun.s32    d5, q15, #7
 
     ; saturate
-    vqshrn.u16      d2, q1, #0
-    vqshrn.u16      d3, q2, #0
+    vqmovn.u16      d2, q1
+    vqmovn.u16      d3, q2
 
     vst1.u32        {d2[0]}, [r2], r3
     vst1.u32        {d2[1]}, [r2], r3