Change-Id: Ibad1dc5bf0e9ad13b5823cebfb599b10baad635c

Update the OBU parser to shift OBU header values before
masking instead of the opposite, and rename constants for
clarity.

Change-Id: Iea91fad7e825697573f255f450a3605b65c657f7

max-tile remains off by default until more testing is performed but I would
like to check in the fixes that are known so far to prevent this patch getting too big

max_tile was provisionally adopted at the working group meeting 2017-Oct-10

This patch fixes the following issues:
- max_tile is fixed to suport superblock size 64x64 as well as 128x128 (ext_partition support)
- max_tile is fixed in combination with loop_restoration
- max_tile is fixed in combination with ext_tile (Bug: 1013)
- max_tile is fixed in combination with lv_map and 64x64 subperblock (lv_map memory allocation
  fixed for 64x64 superblock)
- max_tile reports the size of the first tile for inspection.c used by the analyzer

Change-Id: Ib83ff613e5d66563c81452a085c7984d3b4813e4

Change-Id: I8c739c9b1911b983a14772d79e0c7c28373fdca2

nasm should infer .text but does not for windows:
https://bugzilla.nasm.us/show_bug.cgi?id=3392451

Based on libvpx bdbecea

Change-Id: If4f8ecdd7d7ce3e9c5b5286a6422cc954da10d15

Don't add include files to the archive. Avoids build failures for
Windows such as:
the input file 'libvpx_g.a(x86_abi_support.asm.o)' has no sections

Cherry picked from libvpx e83d00f

Change-Id: I3dce787901e6285cebc46029c20ad3993039150d

No need to specify default behaviour. The original change introducing nasm:
https://chromium.googlesource.com/webm/libvpx/+/7be093ea4d50c8d38438f88cb9fa817c1c9de8dd
mentions requiring 2.0.9, which was the first release to default to this behaviour:
http://www.nasm.us/doc/nasmdoc2.html
"The -Ox mode is recommended for most uses, and is the default since NASM 2.09."

Cherry picked from libvpx 65df957 and cmake updated.

Change-Id: Ie860b37d070b0fbd7f61d20f527396ee796e826f

nasm does not accept x64

yasm has accepted (and appears to prefer) win64 at least as far back as
1.0.0:
http://yasm.tortall.net/releases/Release1.0.0.html

Cherry picked from libvpx 460dbc0

Change-Id: I603981be6379732f5b8d5940294a79cef4b16c89

arm finishes assembly files with END but x86 does not.

Cleans warning when building with nasm:
warning: label alone on a line without a colon might be in error

Change-Id: I048ef08f5183356bc0f44d0464110b284dd754b9

This experiment has been abandonned for AV1.

Change-Id: Ief159fa7cf41dafa1e71b140f585cbc5a7d0a67d

Drop unnecessary ref_mvs assignment steps in the rate-distortion
optimization process.

Change-Id: Icbd0436d2f962ec6b1141b889cf5892b863f081d

Re-design the dynamic motion vector index coding system to remove
the context parsing dependency on the reconstructed motion vectors.

Change-Id: I01dd6eda239a0bed32d8dc98f0f10f18249a76d4

BUG=aomedia:1098

Change-Id: If7086930520d740d2610adeb699b68cdafab3ed3

Change-Id: I3923c7e8a41c33dfdb6c3b6f584abe8ab636ed5a

This experiment has been abandonned for AV1.

Change-Id: I8110720cef1b56dbce4008a998d8f4281dd2fe44

Change-Id: I701f3a279c5b0f64df10b9c5daae8dd10498080b

Change-Id: I5c232b6948b236136aed609532d4cdf4a7016e4d

Change-Id: Ia190c8b70173b48c91ae0dbb12d007c2a3f5d9b9

This patch fixes and enables rectangular intra transform
sizes for 4:1 partitions (that were turned off before).
4:1 partitions can now use rectangular intra predictions with
2:1 rectangular transform sizes.
BDRATE lowres (single keyframe): -0.612%

Change-Id: I6f062f7c08aae8eeb0a55d31e792c8f7e3f302a2

These don't share the same kernel functions as the others so we can
avoid doing two transposes for the rows and because we don't need
to split short rows into multiple registers for the columns.

The resulting IDTX implementations can be re-used for all sizes,
though we might benefit from the larger AVX registers for the
larger sizes.

It might also be worth having a fast path for IDTX_IDTX to avoid an
extra round-trip through memory, but that can be added in a
separate patch if it proves worthwhile.

Change-Id: I36fa4ea44c7dd2c165bff750d9bc8a213783041f

Despite the function pointers used to avoid copying and pasting the
boilerplate code around each transform kernel, the compiler will
inline everything to straightline code, with all SIMD parameters
kept in registers.

Change-Id: I3a89d6499e1972967dcccf397507676ee57ee33b

This fixes a potential overflow when using the 4-point Type VII DST
as the row transform in a 4x16 transform block.

Results on subset1:

https://arewecompressedyet.com/?job=%402017-12-03T01%3A27%3A43.842Z&job=%402017-12-03T01%3A27%3A43.842Z%402017-12-03T01%3A29%3A23.170Z

  PSNR | PSNR HVS |   SSIM | MS SSIM | CIEDE 2000
0.0113 |   0.0367 | 0.0063 |  0.0013 |     0.0182

Change-Id: Ib8ca6a2e06cd7d1b625cbbadcded2488eececd9c

Currently this only requires SSSE3 operations, but we build it as
AVX2 to get support for 3-operand instructions. Separate versions
for different instruction sets will be added later.

Change-Id: Ib02c1496832923ecf6dccc1a208dc5ac5559dad2

This calls the C version of the transforms and verifies that the
SIMD is a bit-exact match on every invocation. It must be manually
enabled by editing the code to define DAALA_TX_VERIFY_SIMD. This is
intended to be replaced by real unit tests in the future.

Change-Id: I2c09c8a476cce21a9f48f9d7120185bfa7af42aa

This just adds a top-level daala_inv_txfm_add_avx2(), but no actual
SIMD functions yet. It dispatches back to the C version for all TX
types and sizes for the moment.

Change-Id: I7a578a4af363f989615d01ea67ce031d8ceff977

This commit re-structures the speed feature setup for the codec
development purpose. Instead of progressively reducing encoder
complexity at the expense of incremental coding loss, we allow a
separate set of speed features, each corresponds to a certain
category of coding units:

1 << 0: transform coding
1 << 1: inter prediction
1 << 2: intra prediction
1 << 3: block partition
1 << 4: loop filters
1 << 5: rd early skip

[6 - 7] are left open for next adjustment.

It is constructed to facilitate the codec development purpose.
When working on a coding functions, one could choose to turn on
one or more less related coding units to speed up the evaluation
process. For example, to test a transform related experiment, one
could set
--dev-sf=2, 6, or 22
which corresponds to turning on:
2 - inter prediction speed features,
6 - both inter / intra speed features,
22 - inter / intra, and loop filter features.

The goal is to allow faster experimental verification during the
development process. With the experiment in a stable state, we
can evaluate its performance in speed 0 at higher confidence level.

Change-Id: Ib46c7dea2d2a60204c399dc01f10262c976adf0d

When this is set (use --monochrome), all decoded frames
will be given constant chroma planes.

If the rawvideo option is used in conjunction with the
monochrome option (i.e. --monochrome --rawvideo), the
written output will only consist of the Y (luma) plane.

Change-Id: I967817f1c3ebb1162fa9771b51cf6431120b835c

This commit resolves the inter mode context model dependency on
the reconstructed motion vectors.

Change-Id: I3fd885dba6c10be8b1dcd072c1a5b3925ef4d1f5

remove tmp0 in update_cdf due to the use of EC_MIN_PROB introduced by
Thomas Davies.

further changes to update_cdf include:
1. Start the rate at 3+get_msb(nsymbs) and increase the rate by one at
counts 16 and 32.
2. Check if tmp is less than cdf[i] to avoid shifting a negative number.

Change-Id: I5088ebd450d6e57ec6c3e92bb2f47a078489b947

Change-Id: I2ad279d27fb34c9c6bcee6029a40377541f066a7

TX64X64 uses 32x32 coeff buffer

Change-Id: Ied4279807207176d590af4c1fc4bb648a618d158

Change-Id: I717bcec45e061e9685c00282f1c2a4d53a3481ef

This will make txk_sel support maximum bsize to 128x128

Change-Id: I33941966cb1ae4406ac68a2124c859c833a084d8

Change-Id: I72a01937abc3ad5a1ddd5f5ef1ea79e2320343ad

This 8-point Type-IV DST uses the same computation graph as the
 asymmetric 8-point Type-IV DST with the following changes:

  - The fDST and iDST contain different multiplication constants
  - The fDST does not reuse the passed shifts in the first additions
  - The iDST does not have any OD_RSHIFT1(t_) on the last additions

This reused computation structure could be later pulled into a macro or
 exploited by a hardware implementation.

Change-Id: Iac09c29549ce5dcf7752f71e9e6d24609e7b018a

This is a work in progress. So far this tool supports only
reading of OBU headers with and without extensions. OBU
payload parsing will be added in future commits.

Change-Id: Ie4c184ad4ae8e536e00015e9bde6a7cde8dada28

Change-Id: I64eccc4ce8f2a0f6884bb6f35f4b74ce00b25a30

subset-1:

daala_tx@2017-12-02T19:45:07.284Z -> new_dct16@2017-12-02T20:45:01.824Z

   PSNR | PSNR Cb | PSNR Cr | PSNR HVS |    SSIM | MS SSIM | CIEDE 2000
-0.0179 | -0.0640 |  0.0507 |  -0.0464 | -0.0246 | -0.0304 |    -0.0122

Change-Id: Id9f90f1cec7f0948d456c7b0b3564c0b2bd1ac3c

Change-Id: Ida7e054d3e8eedc9e134f0a595072c8cd50e74f9

Change-Id: Ifa0b0c56fd1454d6c856486c96092ed1d3f1b4b9