1. 26 Oct, 2011 1 commit
    • Attila Nagy's avatar
      Reduce partial frame copy in encoder's pick_filter_level_fast · de828094
      Attila Nagy authored
      The partial frame copy function used to copy an extra 8 lines above
      and  below. The partial frame filtering can only modify 3 pixel rows
      above the partial frame. Reduce copy to bare minimum needed, which is
      4 lines, so that partial filtering on copied frame is possible.
      
      Define the "magic" fraction number for partial filtering in
      loopfilter.h .
      
      Change-Id: I4791ffc541b6884b12759a0d0714a8faf16147ec
      de828094
  2. 14 Oct, 2011 1 commit
    • Attila Nagy's avatar
      Fix: vp8cx_pack_tokens_into_partitions_armv5 crash · a5cd42fe
      Attila Nagy authored
      It was crashing when number of partitions was bigger than the number
      of MB rows (ex. 128x96 with 8 partitions).
      Start point was not checked against mb_rows, plus extra
      "empty" partitions were not written out.
      
      Change-Id: I9c2f013b9ec022354b658fab4ef799ff8b1de93d
      a5cd42fe
  3. 22 Sep, 2011 1 commit
  4. 20 Sep, 2011 3 commits
    • Fritz Koenig's avatar
      Move neon only arm functions under arm/neon. · bd0c3409
      Fritz Koenig authored
      These files don't contain generic arm code, so should
      only be compiled by neon.
      
      Change-Id: Ie712823aa04d4235e7cfe7a3b725e73ee4c3e564
      bd0c3409
    • Tero Rintaluoma's avatar
      NEON FDCT updated to match current C code · 0c2529a8
      Tero Rintaluoma authored
      - Removed fast_fdct4x4_neon and fast_fdct8x4_neon
      - Uses now short_fdct4x4 and short_fdct8x4
      - Gives ~1-2% speed-up on Cortex-A8/A9
      
      Change-Id: Ib62f2cb2080ae719f8fa1d518a3a5e71278a41ec
      0c2529a8
    • Tero Rintaluoma's avatar
      Fixed armv5te multiplications · 3c19bc3f
      Tero Rintaluoma authored
      Rd and Rm registers should be different in 'mul'. This register
      combination results in unpredictable behaviour. GCC will give
      a warning and RVCT an error in this case.
      
      Restriction applies only to armv5 targets and not for armv6 and above.
      
      Change-Id: I378d17c51e1f16a6820814fbed43e115aaabb03e
      3c19bc3f
  5. 19 Sep, 2011 2 commits
    • Tero Rintaluoma's avatar
      Updated ARMv6 forward transforms to match C · 4c3ad66b
      Tero Rintaluoma authored
      - Updated walsh transform to match C
        (based on Change Id24f3392)
      - Changed fast_fdct4x4 and 8x4 to short_fdct4x4 and 8x4
        correspondingly
      
      Change-Id: I704e862f40e315b0a79997633c7bd9c347166a8e
      4c3ad66b
    • Tero Rintaluoma's avatar
      NEON walsh transform updated to match C · 2a4b2a00
      Tero Rintaluoma authored
      Modified original patch If2f07220885c4c3a0cae0dace34ea0e36124f001
      according to comments. Scheduled code a little bit to prevent some
      interlocks.
      
      Change-Id: I338f02b881098782f82af63d97f042b85e63e902
      2a4b2a00
  6. 29 Jun, 2011 1 commit
  7. 09 Jun, 2011 1 commit
  8. 06 Jun, 2011 1 commit
    • Yaowu Xu's avatar
      remove redundant functions · d4700731
      Yaowu Xu authored
      The encoder defined about 4 set of similar functions to calculate sum,
      variance or sse or a combination of them. This commit removed one set
      of these functions, get8x8var and get16x16var, where calls to the later
      function are replaced with var16x16 by using the fact on a 16x16 MB:
          variance == sse - sum*sum/256
      
      Change-Id: I803eabd1fb3ab177780a40338cbd596dffaed267
      d4700731
  9. 01 Jun, 2011 1 commit
    • Tero Rintaluoma's avatar
      neon fast quantize block pair · 61f0c090
      Tero Rintaluoma authored
      vp8_fast_quantize_b_pair_neon function added to quantize
      two adjacent blocks at the same time to improve performance.
       - Additional 3-6% speedup compared to neon optimized fast
         quantizer (Tanya VGA@30fps, 1Mbps stream, cpu-used=-5..-16)
      
      Change-Id: I3fcbf141e5d05e9118c38ca37310458afbabaa4e
      61f0c090
  10. 30 May, 2011 1 commit
    • Tero Rintaluoma's avatar
      adds preload for armv6 encoder asm · 5305e79e
      Tero Rintaluoma authored
      Added preload instructions to armv6 encoder optimizations.
      About 5% average speed-up on Tegra2 for VGA@30fps sequence.
      
      Change-Id: I41d74737720fb71ce7a316f07555357822f3347e
      5305e79e
  11. 25 May, 2011 1 commit
  12. 06 May, 2011 1 commit
    • Tero Rintaluoma's avatar
      neon fast quantizer updated · 33fa7c4e
      Tero Rintaluoma authored
      vp8_fast_quantize_b_neon function updated and further optimized.
       - match current C implementation of fast quantizer
       - updated to use asm_enc_offsets for structure members
       - updated ads2gas scripts to handle alignment issues
      
      Change-Id: I5cbad9c460ad8ddb35d2970a8684cc620711c56d
      33fa7c4e
  13. 01 Apr, 2011 1 commit
    • Tero Rintaluoma's avatar
      Wrapper function removed from vp8_subtract_b_neon function call · cec76a36
      Tero Rintaluoma authored
      Address calculations moved from encodemb_arm.c file to neon
      optimized assembly function to save cycles in function calls.
       - vp8_subtract_b_neon_func replaced with vp8_subtract_b_neon
         that contains all needed address calculations
       - unnecessary file encodemb_arm.c removed
       - consistent with ARMv6 optimized version
      
      Change-Id: I6cbc1a2670b56c2077f59995fcf8f70786b4990b
      cec76a36
  14. 29 Mar, 2011 1 commit
    • Tero Rintaluoma's avatar
      ARMv6 optimized subtract functions · 6fdc9aa7
      Tero Rintaluoma authored
      Adds following ARMv6 optimized functions to encoder:
        - vp8_subtract_b_armv6
        - vp8_subtract_mby_armv6
        - vp8_subtract_mbuv_armv6
      
      Gives 1-5% speed-up depending on input sequence and encoding
      parameters. Functions have one stall cycle inside the loop body
      on Cortex pipeline.
      
      Change-Id: I19cca5408b9861b96f378e818eefeb3855238639
      6fdc9aa7
  15. 28 Mar, 2011 1 commit
    • Tero Rintaluoma's avatar
      Half pixel variance further optimized for ARMv6 · f5e43346
      Tero Rintaluoma authored
      Half pixel interpolations optimized in variance calculations. Separate
      function calls to vp8_filter_block2d_bil_x_pass_armv6 are avoided.On
      average, performance improvement is 6-7% for VGA@30fps sequences.
      
      Change-Id: Idb5f118a9d51548e824719d2cfe5be0fa6996628
      f5e43346
  16. 21 Mar, 2011 1 commit
    • Tero Rintaluoma's avatar
      ARMv6 optimized fdct4x4 · a61785b6
      Tero Rintaluoma authored
      Optimized fdct4x4 (8x4) for ARMv6 instruction set.
        - No interlocks in Cortex-A8 pipeline
        - One interlock cycle in ARM11 pipeline
        - About 2.16 times faster than current C-code compiled with -O3
      
      Change-Id: I60484ecd144365da45bb68a960d30196b59952b8
      a61785b6
  17. 15 Mar, 2011 1 commit
  18. 14 Mar, 2011 1 commit
  19. 11 Mar, 2011 1 commit
    • Tero Rintaluoma's avatar
      ARMv6 optimized quantization · 7ab08e1f
      Tero Rintaluoma authored
      Adds new ARMv6 optimized function vp8_fast_quantize_b_armv6
      to the encoder.
      
      Change-Id: I40277ec8f82e8a6cbc453cf295a0cc9b2504b21e
      7ab08e1f
  20. 23 Feb, 2011 1 commit
    • Tero Rintaluoma's avatar
      ARMv6 optimized half pixel variance calculations · 8ae92aef
      Tero Rintaluoma authored
      Adds following ARMv6 optimized functions to the encoder:
       - vp8_variance_halfpixvar16x16_h_armv6
       - vp8_variance_halfpixvar16x16_v_armv6
       - vp8_variance_halfpixvar16x16_hv_armv6
      
      Change-Id: I1e9c2af7acd2a51b72b3845beecd990db4bebd29
      8ae92aef
  21. 18 Feb, 2011 1 commit
  22. 11 Feb, 2011 1 commit
    • Tero Rintaluoma's avatar
      ARMv6 optimized sad16x16 · 1ef86980
      Tero Rintaluoma authored
      Adds a new ARMv6 optimized function vp8_sad16x16_armv6 to encoder.
      
      Change-Id: Ibbd7edb8b25cb7a5b522d391b1e9a690fe150e57
      1ef86980
  23. 10 Feb, 2011 1 commit
    • John Koleszar's avatar
      Fix relative include paths · 02321de0
      John Koleszar authored
      Allow compiling without adding vp8/{common,encoder,decoder} to the
      include paths.
      
      Change-Id: Ifeb5dac351cdfadcd659736f5158b315a0030b6c
      02321de0
  24. 09 Feb, 2011 1 commit
    • Tero Rintaluoma's avatar
      Adds armv6 optimized variance calculation · cb14764f
      Tero Rintaluoma authored
      Adds vp8_sub_pixel_variance16x16_armv6 function to encoder. Integrates
      ARMv6 optimized bilinear interpolations from vp8/common/arm/armv6
      and adds new assembly file for variance16x16 calculation.
       - vp8_filter_block2d_bil_first_pass_armv6   (integrated)
       - vp8_filter_block2d_bil_second_pass_armv6  (integrated)
       - vp8_variance16x16_armv6 (new)
       - bilinearfilter_arm.h (new)
      Change-Id: I18a8331ce7d031ceedd6cd415ecacb0c8f3392db
      cb14764f
  25. 08 Feb, 2011 1 commit
    • Johann's avatar
      clarify *_offsets.asm differences · 40dcae9c
      Johann authored
      it's difficult to mux the *_offsets.c files because of header conflicts.
      make three instead, name them consistently and partititon the contents
      to allow building them as required.
      
      Change-Id: I8f9768c09279f934f44b6c5b0ec363f7943bb796
      40dcae9c
  26. 28 Jan, 2011 1 commit
    • Tero Rintaluoma's avatar
      Adds "armvX-none-rvct" targets · 11a222f5
      Tero Rintaluoma authored
      Adds following targets to configure script to support RVCT compilation
      without operating system support (for Profiler or bare metal images).
       - armv5te-none-rvct
       - armv6-none-rvct
       - armv7-none-rvct
      
      To strip OS specific parts from the code "os_support"-config was added
      to script and CONFIG_OS_SUPPORT flag is used in the code to exclude OS
      specific parts such as OS specific includes and function calls for
      timers and threads etc. This was done to enable RVCT compilation for
      profiling purposes or running the image on bare metal target with
      Lauterbach.
      
      Removed separate AREA directives for READONLY data in armv6 and neon
      assembly files to fix the RVCT compilation. Otherwise
      "ldr <reg>, =label" syntax would have been needed to prevent linker
      errors. This syntax is not supported by older gnu assemblers.
      
      Change-Id: I14f4c68529e8c27397502fbc3010a54e505ddb43
      11a222f5
  27. 27 Jan, 2011 1 commit
    • Johann's avatar
      clean up implicit declaration warnings for neon · 27000ed6
      Johann authored
      Change-Id: I6ca2d89f355839c4c770773c09fc69dcea7c1406
      warning: implicit declaration of function
        'vp8_variance_halfpixvar16x16_[h|v|hv]_neon'
        'vp8_sub_pixel_variance16x16_neon_func'
      27000ed6
  28. 25 Jan, 2011 2 commits
  29. 18 Jan, 2011 1 commit
    • Yunqing Wang's avatar
      Modify calling of NEON code in sub-pixel search · ce6c954d
      Yunqing Wang authored
      In vp8_find_best_sub_pixel_step_iteratively(), many times xoffset
      and yoffset are specific values - (4,0) (0,4) and (4,4). Modified
      code to call simplified NEON version at these specific offsets to
      help with the performance.
      
      Change-Id: Iaf896a0f7aae4697bd36a49e182525dd1ef1ab4d
      ce6c954d
  30. 28 Dec, 2010 1 commit
    • Scott LaVarnway's avatar
      Use the fast quantizer for inter mode selection · 516ea846
      Scott LaVarnway authored
      Use the fast quantizer for inter mode selection and the
      regular quantizer for the rest of the encode for good quality,
      speed 1.  Both performance and quality were improved.  The
      quality gains will make up for the quality loss mentioned in
      I9dc089007ca08129fb6c11fe7692777ebb8647b0.
      
      Change-Id: Ia90bc9cf326a7c65d60d31fa32f6465ab6984d21
      516ea846
  31. 14 Dec, 2010 1 commit
    • Johann's avatar
      shrink TOKENEXTRA and vp8_extra_bit_struct · 825adc46
      Johann authored
      Per John's previous change, shrink TOKENEXTRA from 20 to 8 bytes
      original: b7b1e6fb
      reverted: 41f4458a
      
      Also drop unused field from vp8_extra_bit_struct
      
      Update ARM ASM to deal with this change. In particular, Extra is signed
      and needs to be sign-extended when loaded.
      
      Change-Id: Ibd0ddc058432bc7bb09222d6ce4ef77e93a30b41
      825adc46
  32. 27 Oct, 2010 2 commits
    • John Koleszar's avatar
      Fix half-pixel variance RTCD functions · a0ae3682
      John Koleszar authored
      This patch fixes the system dependent entries for the half-pixel
      variance functions in both the RTCD and non-RTCD cases:
      
        - The generic C versions of these functions are now correct.
          Before all three cases called the hv code.
      
        - Wire up the ARM functions in RTCD mode
      
        - Created stubs for x86 to call the optimized subpixel functions
          with the correct parameters, rather than falling back to C
          code.
      
      Change-Id: I1d937d074d929e0eb93aacb1232cc5e0ad1c6184
      a0ae3682
    • John Koleszar's avatar
      Add half-pixel variance RTCD functions · 209d82ad
      John Koleszar authored
      NEON has optimized 16x16 half-pixel variance functions, but they
      were not part of the RTCD framework. Add these functions to RTCD,
      so that other platforms can make use of this optimization in the
      future and special-case ARM code can be removed.
      
      A number of functions were taking two variance functions as
      parameters. These functions were changed to take a single
      parameter, a pointer to a struct containing all the variance
      functions for that block size. This provides additional flexibility
      for calling additional variance functions (the half-pixel special
      case, for example) and by initializing the table for all block sizes,
      we don't have to construct this function pointer table for each
      macroblock.
      
      Change-Id: I78289ff36b2715f9a7aa04d5f6fbe3d23acdc29c
      209d82ad
  33. 26 Oct, 2010 2 commits
    • John Koleszar's avatar
      make arm hex search the generic implementation · 96cf6588
      John Koleszar authored
      The ARM version of vp8_hex_search() is a faster implementation
      of the same algorithm. Since it doesn't use any ARM specific
      code, it can be made the default implementation. This removes
      a linking error.
      
      Change-Id: I77d10f2c16b2515bff4522c350004e03b7659934
      96cf6588
    • John Koleszar's avatar
      arm: remove duplicate functions · d330a587
      John Koleszar authored
      These functions were true duplicates of functions present in the
      generic code. This fixes some of the link errors when building
      with --enable-shared --enable-pic.
      
      Change-Id: Idff26599d510d954e439207883607ad6b74df20c
      d330a587
  34. 25 Oct, 2010 1 commit
    • Timothy B. Terriberry's avatar
      Add runtime CPU detection support for ARM. · b71962fd
      Timothy B. Terriberry authored
      The primary goal is to allow a binary to be built which supports
       NEON, but can fall back to non-NEON routines, since some Android
       devices do not have NEON, even if they are otherwise ARMv7 (e.g.,
       Tegra).
      The configure-generated flags HAVE_ARMV7, etc., are used to decide
       which versions of each function to build, and when
       CONFIG_RUNTIME_CPU_DETECT is enabled, the correct version is chosen
       at run time.
      In order for this to work, the CFLAGS must be set to something
       appropriate (e.g., without -mfpu=neon for ARMv7, and with
       appropriate -march and -mcpu for even earlier configurations), or
       the native C code will not be able to run.
      The ASFLAGS must remain set for the most advanced instruction set
       required at build time, since the ARM assembler will refuse to emit
       them otherwise.
      I have not attempted to make any changes to configure to do this
       automatically.
      Doing so will probably require the addition of new configure options.
      
      Many of the hooks for RTCD on ARM were already there, but a lot of
       the code had bit-rotted, and a good deal of the ARM-specific code
       is not integrated into the RTCD structs at all.
      I did not try to resolve the latter, merely to add the minimal amount
       of protection around them to allow RTCD to work.
      Those functions that were called based on an ifdef at the calling
       site were expanded to check the RTCD flags at that site, but they
       should be added to an RTCD struct somewhere in the future.
      The functions invoked with global function pointers still are, but
       these should be moved into an RTCD struct for thread safety (I
       believe every platform currently supported has atomic pointer
       stores, but this is not guaranteed).
      
      The encoder's boolhuff functions did not even have _c and armv7
       suffixes, and the correct version was resolved at link time.
      The token packing functions did have appropriate suffixes, but the
       version was selected with a define, with no associated RTCD struct.
      However, for both of these, the only armv7 instruction they actually
       used was rbit, and this was completely superfluous, so I reworked
       them to avoid it.
      The only non-ARMv4 instruction remaining in them is clz, which is
       ARMv5 (not even ARMv5TE is required).
      Considering that there are no ARM-specific configs which are not at
       least ARMv5TE, I did not try to detect these at runtime, and simply
       enable them for ARMv5 and above.
      
      Finally, the NEON register saving code was completely non-reentrant,
       since it saved the registers to a global, static variable.
      I moved the storage for this onto the stack.
      A single binary built with this code was tested on an ARM11 (ARMv6)
       and a Cortex A8 (ARMv7 w/NEON), for both the encoder and decoder,
       and produced identical output, while using the correct accelerated
       functions on each.
      I did not test on any earlier processors.
      
      Change-Id: I45cbd63a614f4554c3b325c45d46c0806f009eaa
      b71962fd