1. 30 Nov, 2012 1 commit
  2. 27 Nov, 2012 1 commit
    • John Koleszar's avatar
      Add vp9_ prefix to all vp9 files · fcccbcbb
      John Koleszar authored
      Support for gyp which doesn't support multiple objects in the same
      static library having the same basename.
      
      Change-Id: Ib947eefbaf68f8b177a796d23f875ccdfa6bc9dc
      fcccbcbb
  3. 01 Nov, 2012 1 commit
  4. 31 Oct, 2012 1 commit
  5. 30 Jan, 2012 1 commit
    • John Koleszar's avatar
      RTCD: add recon functions · fdb61a45
      John Koleszar authored
      This commit continues the process of converting to the new RTCD
      system.
      
      Change-Id: I9bfcf9bef65c3d4ba0fb9a3e1532bad1463a10d6
      fdb61a45
  6. 20 Jan, 2012 1 commit
    • Fritz Koenig's avatar
      Disconnect ARM tgt_isa from dsp extensions · 89210284
      Fritz Koenig authored
      A processor with ARMv7 instructions does not
      necessarily have NEON dsp extensions.  This CL
      has the added side effect of allowing the ability
      to enable/disable the dsp extensions cleanly.
      
      Change-Id: Ie1e879b8fe131885bc3d4138a0acc9ffe73a36df
      89210284
  7. 09 Nov, 2011 1 commit
    • Tero Rintaluoma's avatar
      ARMv6 optimized Intra4x4 prediction · 5a2fd63a
      Tero Rintaluoma authored
      Added ARM optimized intra 4x4 prediction
       - 2x faster on Profiler compared to C-code compiled with -O3
       - Function interface changed a little to improve BLOCKD structure
         access
      
      Change-Id: I9bc2b723155943fe0cf03dd9ca5f1760f7a81f54
      5a2fd63a
  8. 18 Oct, 2011 1 commit
    • Scott LaVarnway's avatar
      Remove usage of predict buffer for decode · ed9c66f5
      Scott LaVarnway authored
      Instead of using the predict buffer, the decoder now writes
      the predictor into the recon buffer.  For blocks with eob=0,
      unnecessary idcts can be eliminated.  This gave a performance
      boost of ~1.8% for the HD clips used.
      
      Tero: Added needed changes to ARM side and scheduled some
            assembly code to prevent interlocks.
      
      Patch Set 6:  Merged (I1bcdca7a95aacc3a181b9faa6b10e3a71ee24df3)
      into this commit because of similarities in the idct
      functions.
      Patch Set 7: EC bug fix.
      
      Change-Id: Ie31d90b5d3522e1108163f2ac491e455e3f955e6
      ed9c66f5
  9. 11 Mar, 2011 1 commit
  10. 27 Oct, 2010 1 commit
  11. 26 Oct, 2010 1 commit
    • John Koleszar's avatar
      make vp8_recon16x16mb{,y} RTCD functions · d6c67f02
      John Koleszar authored
      ARM NEON has a platform specific version of vp8_recon16x16mb, though
      it's just a stub to extract the various parameters from the
      MACROBLOCKD struct and pass them to vp8_recon16x16mb_neon(). Using
      that function's prototype directly will be a better long term solution,
      but it's quite an invasive change.
      
      Change-Id: I04273149e2ade34749e2d09e7edb0c396e1dd620
      d6c67f02
  12. 25 Oct, 2010 1 commit
    • Timothy B. Terriberry's avatar
      Add runtime CPU detection support for ARM. · b71962fd
      Timothy B. Terriberry authored
      The primary goal is to allow a binary to be built which supports
       NEON, but can fall back to non-NEON routines, since some Android
       devices do not have NEON, even if they are otherwise ARMv7 (e.g.,
       Tegra).
      The configure-generated flags HAVE_ARMV7, etc., are used to decide
       which versions of each function to build, and when
       CONFIG_RUNTIME_CPU_DETECT is enabled, the correct version is chosen
       at run time.
      In order for this to work, the CFLAGS must be set to something
       appropriate (e.g., without -mfpu=neon for ARMv7, and with
       appropriate -march and -mcpu for even earlier configurations), or
       the native C code will not be able to run.
      The ASFLAGS must remain set for the most advanced instruction set
       required at build time, since the ARM assembler will refuse to emit
       them otherwise.
      I have not attempted to make any changes to configure to do this
       automatically.
      Doing so will probably require the addition of new configure options.
      
      Many of the hooks for RTCD on ARM were already there, but a lot of
       the code had bit-rotted, and a good deal of the ARM-specific code
       is not integrated into the RTCD structs at all.
      I did not try to resolve the latter, merely to add the minimal amount
       of protection around them to allow RTCD to work.
      Those functions that were called based on an ifdef at the calling
       site were expanded to check the RTCD flags at that site, but they
       should be added to an RTCD struct somewhere in the future.
      The functions invoked with global function pointers still are, but
       these should be moved into an RTCD struct for thread safety (I
       believe every platform currently supported has atomic pointer
       stores, but this is not guaranteed).
      
      The encoder's boolhuff functions did not even have _c and armv7
       suffixes, and the correct version was resolved at link time.
      The token packing functions did have appropriate suffixes, but the
       version was selected with a define, with no associated RTCD struct.
      However, for both of these, the only armv7 instruction they actually
       used was rbit, and this was completely superfluous, so I reworked
       them to avoid it.
      The only non-ARMv4 instruction remaining in them is clz, which is
       ARMv5 (not even ARMv5TE is required).
      Considering that there are no ARM-specific configs which are not at
       least ARMv5TE, I did not try to detect these at runtime, and simply
       enable them for ARMv5 and above.
      
      Finally, the NEON register saving code was completely non-reentrant,
       since it saved the registers to a global, static variable.
      I moved the storage for this onto the stack.
      A single binary built with this code was tested on an ARM11 (ARMv6)
       and a Cortex A8 (ARMv7 w/NEON), for both the encoder and decoder,
       and produced identical output, while using the correct accelerated
       functions on each.
      I did not test on any earlier processors.
      
      Change-Id: I45cbd63a614f4554c3b325c45d46c0806f009eaa
      b71962fd
  13. 09 Sep, 2010 1 commit
  14. 18 Jun, 2010 1 commit
    • John Koleszar's avatar
      cosmetics: trim trailing whitespace · 94c52e4d
      John Koleszar authored
      When the license headers were updated, they accidentally contained
      trailing whitespace, so unfortunately we have to touch all the files
      again.
      
      Change-Id: I236c05fade06589e417179c0444cb39b09e4200d
      94c52e4d
  15. 04 Jun, 2010 1 commit
  16. 18 May, 2010 1 commit