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This experiment has been abandonned for AV1.

Change-Id: If560a67d00b8ae3daa377a59293d5125a8cb7902

Remove the redundant handle_inter_mode calls from the jnt-comp
encoding route.

Change-Id: I1f4fded525cfd3ead7d06c977ab8d99cb7f02273

BUG=aomedia:1014

Change-Id: I8846432861e9859a00f702407a82d4223c093fe2

Change-Id: Ie392e88609554fea99e74c94812799f72b78725b

This patch adds Daala TX transforms ot the 32x64 and 64x32 transform
block sizes using Q3 (up 4, down 1) scaling.

subset 1:
monty-daalaTX-fulltest-Daalabaseline-s1@2017-11-07T00:01:46.582Z ->
 monty-daalaTX-LBD-Daala32x64-s1-Z@2017-11-07T06:10:58.523Z

  PSNR | PSNR Cb | PSNR Cr | PSNR HVS |   SSIM | MS SSIM | CIEDE 2000
0.0112 | -0.0769 |  0.0799 |   0.0567 | 0.0099 | -0.0077 |    -0.0446

objective 1 fast:
monty-daalaTX-fulltest-Daalabaseline-o1f4@2017-11-07T05:59:16.553Z ->
 monty-daalaTX-LBD-Daala32x64-o1f4-Z@2017-11-07T06:10:11.519Z

   PSNR | PSNR Cb | PSNR Cr | PSNR HVS |    SSIM | MS SSIM | CIEDE 2000
-0.0190 |  0.0926 | -0.0730 |  -0.0516 | -0.0037 | -0.0588 |     0.1310

Change-Id: I6246ecba388ae81deadc7b306dc3404fa7869aab

Generalize quantizer setup so that quantization and TX can use
different coefficient shifts/scalings without inpacting RDO lambda
generation.

This patch is documentaiton + a minor refactor setting up later
work; it causes no functional change.

monty-daalaTX-fulltest-Daalabaseline-o1f@2017-11-07T00:01:20.779Z ->
 monty-daalaTX-fulltest-DaalaRDO-o1f@2017-11-07T00:02:31.347Z

PSNR | PSNR Cb | PSNR Cr | PSNR HVS | SSIM | MS SSIM | CIEDE 2000
 N/A |  0.0000 |  0.0000 |      N/A |  N/A |     N/A |        N/A
(note-- the numbers above were collected using --cpu-used=3, which
 appears to be newly broken.)

monty-daalaTX-fulltest-Daalabaseline-o1f4@2017-11-07T05:59:16.553Z ->
 monty-daalaTX-fulltest-DaalaRDO-o1f4@2017-11-07T05:59:50.180Z

  PSNR | PSNR Cb | PSNR Cr | PSNR HVS |   SSIM | MS SSIM | CIEDE 2000
0.0000 |  0.0000 |  0.0000 |   0.0000 | 0.0000 |  0.0000 |     0.0000

monty-daalaTX-fulltest-Daalabaseline-s1@2017-11-07T00:01:46.582Z ->
 monty-daalaTX-fulltest-DaalaRDO-s1@2017-11-07T00:02:56.282Z

  PSNR | PSNR Cb | PSNR Cr | PSNR HVS |   SSIM | MS SSIM | CIEDE 2000
0.0000 |  0.0000 |  0.0000 |   0.0000 | 0.0000 |  0.0000 |     0.0000

Change-Id: Ia5a3c052eacd17184ca1b0fe6d032cfb9afdb77f

To skip possible unnecessary looping.

Change-Id: If611d344ab39eee53de6c5256ce5f8febedecc9b

Change-Id: Idb4c986d8cd795e2d2ea76023674c8b2ba5d353c

This patch is to add the according changes to update_stats() on the
encoder side for signaling of delta_qindex and delta_lflevel, aligned
with the following CL:
https://aomedia-review.googlesource.com/c/aom/+/30801

BUG=aomedia:992

Change-Id: Ie627d4ebce085da85bcee7d5d3f9a7c358725481

Change-Id: Ied50f8302875ce03a4e52ff8862422d8ec919c7f

Change-Id: I04560ea2893087b0485133d7a123ceb594d9d0d2

Change-Id: Ib5de3d1c1acce676b3fcc12b4c237d681ac9a845

Change-Id: If0b45997af5c0b209b48db9bd78ed6be204acb7c

This will facilitate later experiments reducing the precision
of probabilities.

after_cdf_table_rewrite-3 -> before_cdf_table_rewrite-3

  PSNR | PSNR Cb | PSNR Cr | PSNR HVS |   SSIM | MS SSIM | CIEDE 2000
0.0000 |  0.0000 |  0.0000 |   0.0000 | 0.0000 |  0.0000 |     0.0000

Change-Id: Ief01b4d7fdca075c41e9add079f7ac836dafcfbe

Soft enabled TMV to realize the decoder speedup.

Change-Id: Id8ca3e82b3cad968dc795badc40a53ef87376615

Encoder:
Use oxcf->width/heigth instead of cm->width/height in sequence header.
aom_internal_error() if cm->width/height is larger than max values.

Decoder:
aom_internal_error() if cm->width/height is larger than max values.

Change-Id: I8d8b415efe82d961dbe34377f4da79379cb111a8

Fix an issue of sudden PSNR drop on a few frames when convolve_round
is turned on.

C functions is added.

Corresponding simd functions and unit tests will be updated in
future CL.

Change-Id: I0126ea4d54c98951e5b1efeaecd5468fdc18724a

av1_apply_encoding_flags() was called in encoder_encode(). If
lag_in_frames > 0, it wouldn't be called for last several frames
while flushing the encoder, and thus cpi->ref_frame_flags can not
be set correctly. This patch fixed the issue by adding an extra
flag cpi->ext_ref_frame_flags to store the external reference
frame flag, and pass it to cpi->ref_frame_flags correctly.

Change-Id: I9c3f22f92b81c7b4b6241a3f7edcaeabd8d8bbc9

Always assume ONE_SIDED_COMPOUND is true as it has been adopted
officially. Further, this patch also fixes the cmake setup for
the experiment of EXT_COMP_REFS, as when EXT_COMP_REFS is on, it
shall always have ONE_SIDED_COMPOUND on (but that was not the case
without this patch).

We leave EXT_COMP_REFS for the time being, even though it is also
adopted, since by keeping this flag, it may allow its turning off to
tune the encoder speed. The experiment of EXT_COMP_REFS should be
removed eventually at the closing of the bitstream.

Change-Id: I0644318e522f5b48d5bba4e4391104a24d43cdc3

This reverts commit ab8bb8b8.

The reverted breaks many nightly run tests, reverting this temporarily
to allow nightly tests to detect other failures. Once the issues are
fixed, we can reenable the change in the reverted commit.

BUG=aomedia:1012
BUG=aomedia:1013
BUG=aomedia:1014

Change-Id: I2503fe78e47c7a08bb6cfdfff2c295cec0b6497d

Change-Id: Ie6d663aacbed1452060cdef60e96d6acf469d430

Change-Id: I8b3e028b3c17660b390ce9c65b3d31aabc83efd9

Change-Id: I48f45d47123c3eeea0684a5652bffec499408095

Change-Id: I853a0e4b5fc7e7b5c1745b401214ef71b65aad60

Change-Id: I26969ab591482dc9a6095059ba8a8935090f6e5e

This seems a little cleaner than having the loop open coded in four
places.

Change-Id: I2ce7be2745ba3575f618d9e261ab767d10f551f7

Teach read_sequence_header_obu and write_sequence_header_obu to just
call read_sequence_header and write_sequence_header, respectively.

Change-Id: Iff27b5cfbccab0ebaf2e28d72df3d6606964936f

It was mixing uint32_t and size_t, which isn't correct on a 64-bit
system and causes compilation warnings.

Change-Id: I3677c02cb366d60175e762ec4249d2445ee729de

Also, factor out some long constants to avoid line wrapping.

BUG=aomedia:1009

Change-Id: I7850c27d22ef8b927c3554f1083bc7bdf2c7c6b3

This experiment has been abandonned for AV1.

Change-Id: I599608060ade646d6551dea7cfc680f83ee9d507

Change-Id: Ibaeea878e37f193e405910fac34176065cb5d2e3

DV and ref DV should not have subpel values.

Change-Id: I7c47c442936f1d6bda36314812c44498ba6195a6

When generating ref mv list, only consider neighbor blocks that use intrabc.

Change-Id: I69f838a38478ce118f936dbf431048d3d42d4f34

av1_txb_init_levels() has prefix 'av1' because it will be optimized
and not static later.

Change-Id: I988da817335f122522a76c4412207c3a6fdd6b71

Provisionally adopted on 2017-10-31

(Also an asan warning fix + few non-functional changes)

Change-Id: I2ff4f34f8b20d2eeb567f2e5b1e57b296a97be82

Change-Id: I21f956a83687ebaeab81577aabdbfed2ea2b4dd2

A speedup feature that enforces the maximum number of reference frames
to evaluate for each arbitrary frame to be 6, as opposed to the maximum
syntax-allowed number of reference frames which is 7, through the
following rules:

(1) When all the possible reference frames are availble, we reduce the
    number of reference frames (7) by 1 by removing one reference
    frame;
(2) Always retain GOLDEN_FARME/ALTEF_FRAME;
(3) Check the earliest 2 remaining reference frames, and there are two
    options to remove one reference frame:
    (a) Remove the one with the lower quality factor; Otherwise if
    both frames have been coded at the same quality level, remove the
    earliest reference frame;
    (b) Always remove the earliest reference frame.
    Currently set option (a).

This patch has demonstrated an encoder speedup of ~8.5%. It is under
speed2 with "selective_ref_frame >= 2". (May be considered to move
to speed1 later once the coding performance impact is evaluated
further.)

Using the following configure setups, the coding performance has been
dropped on Google test sets (50 frames) in BDRate by ~0.2% for lowres
and by ~0.1% for midres:
--enable-experimental --disable-convolve-round --disable-ext-partition
--disable-ext-partition-types --disable-txk-sel --disable-txm

Change-Id: I84317bae00bfd90b2c3d301858a849f441974e6f

Because daala_tx only ever does an unbiased shift by 1, we can replace
 the varible shift macro with a simpler hardcoded implementation.
This patch causes no change in behavior.

subset-1:

daala_tx@2017-11-04T07:20:17.571Z ->
 daala_tx-no_op@2017-11-04T07:21:06.231Z

  PSNR | PSNR Cb | PSNR Cr | PSNR HVS |   SSIM | MS SSIM | CIEDE 2000
0.0000 |  0.0000 |  0.0000 |   0.0000 | 0.0000 |  0.0000 |     0.0000

Change-Id: Ifddfef079320de0df09d9bc39757af9fe81e3c38

The recent 64x32 and 32x64 patches break the build when
CONFIG_DAALA_TX and CONFIG_TX64X64 are enabled simultaneously.  This
is a minor correction that fixes the build problem.

Change-Id: I53cd8df9160fc35b67f2ac16bddcfab08425cf8e

This change seems to drop efficiency more than expected. So backing
that out for now until a better rd based decision is found.

Change-Id: I3791a13ba76cfa38dd0df2f1fd4119b42b12291d