1. 05 Dec, 2017 29 commits
    • Cheng Chen's avatar
      JNT_COMP: divide compound modes into two groups · 33a13d9f
      Cheng Chen authored
      Divide compound inter prediction modes into two groups:
      Group A: jnt_comp, compound_average
      Group B: interintra, compound_segment, wedge
      
      Change-Id: I1142da2e3dfadf382d6b8183a87bde95119cf1b7
      33a13d9f
    • Timothy B. Terriberry's avatar
      daala_tx: Add SIMD version of the 16-point DCT · b0191d21
      Timothy B. Terriberry authored
      Change-Id: Ie3e599def556a90c474680567c4537508de2e30a
      b0191d21
    • Nathan E. Egge's avatar
      daala_tx: New flattened 4-point Type-IV asym DST. · dc857d1b
      Nathan E. Egge authored
      This 4-point Type-IV asymmetric DST uses the same computation graph as
       the 4-point Type-IV DST.
      This change improves the accuracy of the 8-point Type-II DCT:
      
      Old MSE: 1.8927096972341813413041010372151e-06
      New MSE: 1.7946367518072710517065436117146e-06
      
      subset-1:
      
      new_dst4@2017-12-04T06:31:41.096Z -> new_dst4a@2017-12-04T06:32:22.698Z
      
         PSNR | PSNR Cb | PSNR Cr | PSNR HVS |    SSIM | MS SSIM | CIEDE 2000
      -0.0143 |  0.0410 | -0.2166 |  -0.0556 | -0.0379 | -0.0461 |    -0.0002
      
      Change-Id: Ifde11fca987220130c1657306b0df34ec2f3fe25
      dc857d1b
    • Nathan E. Egge's avatar
      daala_tx: New flattened 4-point Type-IV DST. · 4644a7d0
      Nathan E. Egge authored
      This change slightly improves the 16-point DCT round trip accuracy due
       to changes in the rounding.
      
      subset-1:
      
      new_dst2@2017-12-04T01:59:57.412Z -> new_dst4@2017-12-04T06:31:41.096Z
      
        PSNR | PSNR Cb | PSNR Cr | PSNR HVS |   SSIM | MS SSIM | CIEDE 2000
      0.0078 | -0.0001 |  0.0198 |   0.0432 | 0.0408 |  0.0502 |    -0.0057
      
      Change-Id: I75783ace97834af89e70c9ce3002c6f09176e343
      4644a7d0
    • Nathan E. Egge's avatar
      daala_tx: New flattened 2-point Type-IV DST. · ef525df6
      Nathan E. Egge authored
      This 2-point Type-IV DST uses the same computation graph as the
       asymmetric 2-point Type-IV DST.
      Because this transform is embedded, it may be possible to remove the
       initial averaging step by splitting the 2-point Type-IV DST into
       separate forward and inverse transforms.
      This change also reduces two multiplication constants (forward and
       inverse transform) so they are less than 1.
      
      subset-1:
      
      new_dst2a@2017-12-04T01:59:12.884Z -> new_dst2@2017-12-04T01:59:57.412Z
      
         PSNR | PSNR Cb | PSNR Cr | PSNR HVS |    SSIM | MS SSIM | CIEDE 2000
      -0.0126 |  0.0387 |  0.0441 |   0.0554 | -0.0301 |  0.0034 |    -0.0342
      
      Change-Id: I98568e0c5b97e3a6af27653ddab845ce97d2a53d
      ef525df6
    • Nathan E. Egge's avatar
      daala_tx: New flattened 2-point Type-IV asym DST. · 5b69b199
      Nathan E. Egge authored
      This change improves the accuracy of the 4-point Type-II DCT:
      
      Old MSE: 6.2711279572488185887270981198199e-08
      New MSE: 6.0281623825882593130347914239103e-08
      
      It also reduces a multiplication constant so it is less than 1.
      
      subset-1:
      
      daala_tx@2017-12-04T01:58:11.321Z -> new_dst2a@2017-12-04T01:59:12.884Z
      
        PSNR | PSNR Cb | PSNR Cr | PSNR HVS |   SSIM | MS SSIM | CIEDE 2000
      0.0274 |  0.0255 |  0.0969 |  -0.0024 | 0.0274 |  0.0027 |     0.0110
      
      Change-Id: I7c9d389af8e98cb39f3bc5923134b5dfe174ba0a
      5b69b199
    • Timothy B. Terriberry's avatar
      daala_tx: Add 8-wide 32-bit, 16-wide 16-bit SIMD · 695ebacf
      Timothy B. Terriberry authored
      We use the former variant for the 8-point row transforms when the
      number of columns exceeds 8, since the scaling can exceed 16 bits.
      We ues the latter variant for the 8-point column transforms when
      the number of rows exceeds 8, since it allows us to perform twice
      as many transforms in parallel.
      
      Change-Id: Ia2595ad827636342f70c3d5b99cf05c278bd1389
      695ebacf
    • Timothy B. Terriberry's avatar
      daala_tx: Undo manual SIMD multiply expansion · 009946c8
      Timothy B. Terriberry authored
      On x86 there is no PMULHRSD for use in the 32-bit transform
      versions, so the fastest approach is to just do a normal 32-bit
      multiply and manually shift and round. This requires keeping the
      constants in their reduced precision instead of always promoting
      them to Q15.
      
      Change-Id: I76339b5567da3f08f34882a707e0c93122991946
      009946c8
    • Timothy B. Terriberry's avatar
      daala_tx: Make kernels reg- and word-size agnostic · 170c946e
      Timothy B. Terriberry authored
      This creates the mechanism by which we can define multiple versions
      for different instruction sets and word sizes.
      
      This commit makes no functional changes.
      
      Change-Id: If49ebfc989247692df9c501bea05eb811944d52a
      170c946e
    • Timothy B. Terriberry's avatar
      daala_tx: Move SIMD kernels to a separate header · 65fcf55d
      Timothy B. Terriberry authored
      This will aid us in defining multiple versions for different
      instruction sets and word sizes without duplicating all of the
      code.
      
      This commit makes no functional changes.
      
      Change-Id: I7f240281b0e9edba19c2ee17b9ff3ae36400dcc2
      65fcf55d
    • Timothy B. Terriberry's avatar
      daala_tx: Add SIMD versions of 8-point identity TX · beeaef88
      Timothy B. Terriberry authored
      Change-Id: I49e64d3e062c32925abe30118a64a714073fd4d0
      beeaef88
    • Timothy B. Terriberry's avatar
      daala_tx: Add SIMD version of 8-point DST/FlipDST · c9a1a6cd
      Timothy B. Terriberry authored
      This is using the Type IV version with flattened multiplies for
      now, since we've identified some potential 16-bit overflows in the
      Type VII inverse.
      
      Change-Id: Ib79413ea27efac8b0207602001595ae3ac294eae
      c9a1a6cd
    • Timothy B. Terriberry's avatar
      daala_tx: Add SIMD version of the 8-point DCT · 7c47511a
      Timothy B. Terriberry authored
      Change-Id: Ieb20d64e6531960188feb65296acfa952c858043
      7c47511a
    • Nathan E. Egge's avatar
      Use a Type-IV 8-point DST instead of the Type-VII. · 500b33ec
      Nathan E. Egge authored
      Change-Id: I5c9576069e75b0f369fa9db88d05c0342baf8e6d
      500b33ec
    • Linfeng Zhang's avatar
      Delete 1 parameter in a couple of txb functions · 0ff69c63
      Linfeng Zhang authored
      Change-Id: Ibad1dc5bf0e9ad13b5823cebfb599b10baad635c
      0ff69c63
    • Tom Finegan's avatar
      dump_obu: shift then mask. · 2be4e4d1
      Tom Finegan authored
      Update the OBU parser to shift OBU header values before
      masking instead of the opposite, and rename constants for
      clarity.
      
      Change-Id: Iea91fad7e825697573f255f450a3605b65c657f7
      2be4e4d1
    • Dominic Symes's avatar
      max-tile: Fix issues discovered when testing max-tile · 917d6c06
      Dominic Symes authored
      max-tile remains off by default until more testing is performed but I would
      like to check in the fixes that are known so far to prevent this patch getting too big
      
      max_tile was provisionally adopted at the working group meeting 2017-Oct-10
      
      This patch fixes the following issues:
      - max_tile is fixed to suport superblock size 64x64 as well as 128x128 (ext_partition support)
      - max_tile is fixed in combination with loop_restoration
      - max_tile is fixed in combination with ext_tile (Bug: 1013)
      - max_tile is fixed in combination with lv_map and 64x64 subperblock (lv_map memory allocation
        fixed for 64x64 superblock)
      - max_tile reports the size of the first tile for inspection.c used by the analyzer
      
      Change-Id: Ib83ff613e5d66563c81452a085c7984d3b4813e4
      917d6c06
    • Linfeng Zhang's avatar
      Update get_nz_map_ctx() · 8ac4557b
      Linfeng Zhang authored
      Change-Id: I8c739c9b1911b983a14772d79e0c7c28373fdca2
      8ac4557b
    • Johann's avatar
      explicitly label .text sections · 0fff534b
      Johann authored
      nasm should infer .text but does not for windows:
      https://bugzilla.nasm.us/show_bug.cgi?id=3392451
      
      Based on libvpx bdbecea
      
      Change-Id: If4f8ecdd7d7ce3e9c5b5286a6422cc954da10d15
      0fff534b
    • Johann's avatar
      filter out asm includes · e07fc7cd
      Johann authored
      Don't add include files to the archive. Avoids build failures for
      Windows such as:
      the input file 'libvpx_g.a(x86_abi_support.asm.o)' has no sections
      
      Cherry picked from libvpx e83d00f
      
      Change-Id: I3dce787901e6285cebc46029c20ad3993039150d
      e07fc7cd
    • Johann's avatar
      nasm defaults to -Ox · 29b0c186
      Johann authored
      No need to specify default behaviour. The original change introducing nasm:
      https://chromium.googlesource.com/webm/libvpx/+/7be093ea4d50c8d38438f88cb9fa817c1c9de8dd
      mentions requiring 2.0.9, which was the first release to default to this behaviour:
      http://www.nasm.us/doc/nasmdoc2.html
      "The -Ox mode is recommended for most uses, and is the default since NASM 2.09."
      
      Cherry picked from libvpx 65df957 and cmake updated.
      
      Change-Id: Ie860b37d070b0fbd7f61d20f527396ee796e826f
      29b0c186
    • Johann's avatar
      pass 'win64' instead of 'x64' to the assembler · 02869c20
      Johann authored
      nasm does not accept x64
      
      yasm has accepted (and appears to prefer) win64 at least as far back as
      1.0.0:
      http://yasm.tortall.net/releases/Release1.0.0.html
      
      Cherry picked from libvpx 460dbc0
      
      Change-Id: I603981be6379732f5b8d5940294a79cef4b16c89
      02869c20
    • Johann's avatar
      remove spurious END · 8a2c5cb8
      Johann authored
      arm finishes assembly files with END but x86 does not.
      
      Cleans warning when building with nasm:
      warning: label alone on a line without a colon might be in error
      
      Change-Id: I048ef08f5183356bc0f44d0464110b284dd754b9
      8a2c5cb8
    • Sebastien Alaiwan's avatar
      Remove TPL_MV experiment · b0e7c1a2
      Sebastien Alaiwan authored
      This experiment has been abandonned for AV1.
      
      Change-Id: Ief159fa7cf41dafa1e71b140f585cbc5a7d0a67d
      b0e7c1a2
    • Jingning Han's avatar
      Simplify ref_mvs assignment · c3ef32a4
      Jingning Han authored
      Drop unnecessary ref_mvs assignment steps in the rate-distortion
      optimization process.
      
      Change-Id: Icbd0436d2f962ec6b1141b889cf5892b863f081d
      c3ef32a4
    • Jingning Han's avatar
      Re-design drl index coding to remove ctx parsing dep · b56b71ae
      Jingning Han authored
      Re-design the dynamic motion vector index coding system to remove
      the context parsing dependency on the reconstructed motion vectors.
      
      Change-Id: I01dd6eda239a0bed32d8dc98f0f10f18249a76d4
      b56b71ae
    • Jingning Han's avatar
      Extend div_mult from 32 to 64 · d3c04cdd
      Jingning Han authored
      BUG=aomedia:1098
      
      Change-Id: If7086930520d740d2610adeb699b68cdafab3ed3
      d3c04cdd
    • Sebastien Alaiwan's avatar
      Cosmetics · c6d4eb10
      Sebastien Alaiwan authored
      Change-Id: I3923c7e8a41c33dfdb6c3b6f584abe8ab636ed5a
      c6d4eb10
    • Sebastien Alaiwan's avatar
      Remove ANS experiment · b0460fa9
      Sebastien Alaiwan authored
      This experiment has been abandonned for AV1.
      
      Change-Id: I8110720cef1b56dbce4008a998d8f4281dd2fe44
      b0460fa9
  2. 04 Dec, 2017 11 commits
    • Debargha Mukherjee's avatar
      Support 64x16 and 16x64 rect intra transform sizes · b756d247
      Debargha Mukherjee authored
      Change-Id: I701f3a279c5b0f64df10b9c5daae8dd10498080b
      b756d247
    • Luc Trudeau's avatar
      Intra Prediction for 8x32 and 32x8 · d6d6a1d1
      Luc Trudeau authored
      Change-Id: I5c232b6948b236136aed609532d4cdf4a7016e4d
      d6d6a1d1
    • Luc Trudeau's avatar
      Intra Prediction for 4x16 and 16x4 · dd1acdfc
      Luc Trudeau authored
      Change-Id: Ia190c8b70173b48c91ae0dbb12d007c2a3f5d9b9
      dd1acdfc
    • Debargha Mukherjee's avatar
      Fixes to make 4:1 rectangular intra work correctly · d2cfbefb
      Debargha Mukherjee authored
      This patch fixes and enables rectangular intra transform
      sizes for 4:1 partitions (that were turned off before).
      4:1 partitions can now use rectangular intra predictions with
      2:1 rectangular transform sizes.
      BDRATE lowres (single keyframe): -0.612%
      
      Change-Id: I6f062f7c08aae8eeb0a55d31e792c8f7e3f302a2
      d2cfbefb
    • Timothy B. Terriberry's avatar
      daala_tx: Add SIMD versions of 4-point identity TX · f03f543d
      Timothy B. Terriberry authored
      These don't share the same kernel functions as the others so we can
      avoid doing two transposes for the rows and because we don't need
      to split short rows into multiple registers for the columns.
      
      The resulting IDTX implementations can be re-used for all sizes,
      though we might benefit from the larger AVX registers for the
      larger sizes.
      
      It might also be worth having a fast path for IDTX_IDTX to avoid an
      extra round-trip through memory, but that can be added in a
      separate patch if it proves worthwhile.
      
      Change-Id: I36fa4ea44c7dd2c165bff750d9bc8a213783041f
      f03f543d
    • Timothy B. Terriberry's avatar
      daala_tx: Add SIMD versions of 4-point DST/FlipDST · 47f74646
      Timothy B. Terriberry authored
      Despite the function pointers used to avoid copying and pasting the
      boilerplate code around each transform kernel, the compiler will
      inline everything to straightline code, with all SIMD parameters
      kept in registers.
      
      Change-Id: I3a89d6499e1972967dcccf397507676ee57ee33b
      47f74646
    • Timothy B. Terriberry's avatar
      daala_tx: Remove +1/-1 butterflies from 4-point tx · 3f5bbc5e
      Timothy B. Terriberry authored
      This fixes a potential overflow when using the 4-point Type VII DST
      as the row transform in a 4x16 transform block.
      
      Results on subset1:
      
      https://arewecompressedyet.com/?job=%402017-12-03T01%3A27%3A43.842Z&job=%402017-12-03T01%3A27%3A43.842Z%402017-12-03T01%3A29%3A23.170Z
      
        PSNR | PSNR HVS |   SSIM | MS SSIM | CIEDE 2000
      0.0113 |   0.0367 | 0.0063 |  0.0013 |     0.0182
      
      Change-Id: Ib8ca6a2e06cd7d1b625cbbadcded2488eececd9c
      3f5bbc5e
    • Timothy B. Terriberry's avatar
      daala_tx: Add SIMD version of the 4-point DCT · 2e90b44e
      Timothy B. Terriberry authored
      Currently this only requires SSSE3 operations, but we build it as
      AVX2 to get support for 3-operand instructions. Separate versions
      for different instruction sets will be added later.
      
      Change-Id: Ib02c1496832923ecf6dccc1a208dc5ac5559dad2
      2e90b44e
    • Timothy B. Terriberry's avatar
      daala_tx: Add SIMD verification code · 1b65571b
      Timothy B. Terriberry authored
      This calls the C version of the transforms and verifies that the
      SIMD is a bit-exact match on every invocation. It must be manually
      enabled by editing the code to define DAALA_TX_VERIFY_SIMD. This is
      intended to be replaced by real unit tests in the future.
      
      Change-Id: I2c09c8a476cce21a9f48f9d7120185bfa7af42aa
      1b65571b
    • Timothy B. Terriberry's avatar
      daala_tx: Add inverse TX SIMD dispatch · 18c803fa
      Timothy B. Terriberry authored
      This just adds a top-level daala_inv_txfm_add_avx2(), but no actual
      SIMD functions yet. It dispatches back to the C version for all TX
      types and sizes for the moment.
      
      Change-Id: I7a578a4af363f989615d01ea67ce031d8ceff977
      18c803fa
    • Jingning Han's avatar
      Add the speed feature structure for codec dev · b49c6aea
      Jingning Han authored
      This commit re-structures the speed feature setup for the codec
      development purpose. Instead of progressively reducing encoder
      complexity at the expense of incremental coding loss, we allow a
      separate set of speed features, each corresponds to a certain
      category of coding units:
      
      1 << 0: transform coding
      1 << 1: inter prediction
      1 << 2: intra prediction
      1 << 3: block partition
      1 << 4: loop filters
      1 << 5: rd early skip
      
      [6 - 7] are left open for next adjustment.
      
      It is constructed to facilitate the codec development purpose.
      When working on a coding functions, one could choose to turn on
      one or more less related coding units to speed up the evaluation
      process. For example, to test a transform related experiment, one
      could set
      --dev-sf=2, 6, or 22
      which corresponds to turning on:
      2 - inter prediction speed features,
      6 - both inter / intra speed features,
      22 - inter / intra, and loop filter features.
      
      The goal is to allow faster experimental verification during the
      development process. With the experiment in a stable state, we
      can evaluate its performance in speed 0 at higher confidence level.
      
      Change-Id: Ib46c7dea2d2a60204c399dc01f10262c976adf0d
      b49c6aea