1. 25 Jan, 2011 2 commits
  2. 18 Jan, 2011 1 commit
    • Yunqing Wang's avatar
      Modify calling of NEON code in sub-pixel search · ce6c954d
      Yunqing Wang authored
      In vp8_find_best_sub_pixel_step_iteratively(), many times xoffset
      and yoffset are specific values - (4,0) (0,4) and (4,4). Modified
      code to call simplified NEON version at these specific offsets to
      help with the performance.
      
      Change-Id: Iaf896a0f7aae4697bd36a49e182525dd1ef1ab4d
      ce6c954d
  3. 28 Dec, 2010 1 commit
    • Scott LaVarnway's avatar
      Use the fast quantizer for inter mode selection · 516ea846
      Scott LaVarnway authored
      Use the fast quantizer for inter mode selection and the
      regular quantizer for the rest of the encode for good quality,
      speed 1.  Both performance and quality were improved.  The
      quality gains will make up for the quality loss mentioned in
      I9dc089007ca08129fb6c11fe7692777ebb8647b0.
      
      Change-Id: Ia90bc9cf326a7c65d60d31fa32f6465ab6984d21
      516ea846
  4. 14 Dec, 2010 1 commit
    • Johann's avatar
      shrink TOKENEXTRA and vp8_extra_bit_struct · 825adc46
      Johann authored
      Per John's previous change, shrink TOKENEXTRA from 20 to 8 bytes
      original: b7b1e6fb
      reverted: 41f4458a
      
      Also drop unused field from vp8_extra_bit_struct
      
      Update ARM ASM to deal with this change. In particular, Extra is signed
      and needs to be sign-extended when loaded.
      
      Change-Id: Ibd0ddc058432bc7bb09222d6ce4ef77e93a30b41
      825adc46
  5. 27 Oct, 2010 2 commits
    • John Koleszar's avatar
      Fix half-pixel variance RTCD functions · a0ae3682
      John Koleszar authored
      This patch fixes the system dependent entries for the half-pixel
      variance functions in both the RTCD and non-RTCD cases:
      
        - The generic C versions of these functions are now correct.
          Before all three cases called the hv code.
      
        - Wire up the ARM functions in RTCD mode
      
        - Created stubs for x86 to call the optimized subpixel functions
          with the correct parameters, rather than falling back to C
          code.
      
      Change-Id: I1d937d074d929e0eb93aacb1232cc5e0ad1c6184
      a0ae3682
    • John Koleszar's avatar
      Add half-pixel variance RTCD functions · 209d82ad
      John Koleszar authored
      NEON has optimized 16x16 half-pixel variance functions, but they
      were not part of the RTCD framework. Add these functions to RTCD,
      so that other platforms can make use of this optimization in the
      future and special-case ARM code can be removed.
      
      A number of functions were taking two variance functions as
      parameters. These functions were changed to take a single
      parameter, a pointer to a struct containing all the variance
      functions for that block size. This provides additional flexibility
      for calling additional variance functions (the half-pixel special
      case, for example) and by initializing the table for all block sizes,
      we don't have to construct this function pointer table for each
      macroblock.
      
      Change-Id: I78289ff36b2715f9a7aa04d5f6fbe3d23acdc29c
      209d82ad
  6. 26 Oct, 2010 2 commits
    • John Koleszar's avatar
      make arm hex search the generic implementation · 96cf6588
      John Koleszar authored
      The ARM version of vp8_hex_search() is a faster implementation
      of the same algorithm. Since it doesn't use any ARM specific
      code, it can be made the default implementation. This removes
      a linking error.
      
      Change-Id: I77d10f2c16b2515bff4522c350004e03b7659934
      96cf6588
    • John Koleszar's avatar
      arm: remove duplicate functions · d330a587
      John Koleszar authored
      These functions were true duplicates of functions present in the
      generic code. This fixes some of the link errors when building
      with --enable-shared --enable-pic.
      
      Change-Id: Idff26599d510d954e439207883607ad6b74df20c
      d330a587
  7. 25 Oct, 2010 1 commit
    • Timothy B. Terriberry's avatar
      Add runtime CPU detection support for ARM. · b71962fd
      Timothy B. Terriberry authored
      The primary goal is to allow a binary to be built which supports
       NEON, but can fall back to non-NEON routines, since some Android
       devices do not have NEON, even if they are otherwise ARMv7 (e.g.,
       Tegra).
      The configure-generated flags HAVE_ARMV7, etc., are used to decide
       which versions of each function to build, and when
       CONFIG_RUNTIME_CPU_DETECT is enabled, the correct version is chosen
       at run time.
      In order for this to work, the CFLAGS must be set to something
       appropriate (e.g., without -mfpu=neon for ARMv7, and with
       appropriate -march and -mcpu for even earlier configurations), or
       the native C code will not be able to run.
      The ASFLAGS must remain set for the most advanced instruction set
       required at build time, since the ARM assembler will refuse to emit
       them otherwise.
      I have not attempted to make any changes to configure to do this
       automatically.
      Doing so will probably require the addition of new configure options.
      
      Many of the hooks for RTCD on ARM were already there, but a lot of
       the code had bit-rotted, and a good deal of the ARM-specific code
       is not integrated into the RTCD structs at all.
      I did not try to resolve the latter, merely to add the minimal amount
       of protection around them to allow RTCD to work.
      Those functions that were called based on an ifdef at the calling
       site were expanded to check the RTCD flags at that site, but they
       should be added to an RTCD struct somewhere in the future.
      The functions invoked with global function pointers still are, but
       these should be moved into an RTCD struct for thread safety (I
       believe every platform currently supported has atomic pointer
       stores, but this is not guaranteed).
      
      The encoder's boolhuff functions did not even have _c and armv7
       suffixes, and the correct version was resolved at link time.
      The token packing functions did have appropriate suffixes, but the
       version was selected with a define, with no associated RTCD struct.
      However, for both of these, the only armv7 instruction they actually
       used was rbit, and this was completely superfluous, so I reworked
       them to avoid it.
      The only non-ARMv4 instruction remaining in them is clz, which is
       ARMv5 (not even ARMv5TE is required).
      Considering that there are no ARM-specific configs which are not at
       least ARMv5TE, I did not try to detect these at runtime, and simply
       enable them for ARMv5 and above.
      
      Finally, the NEON register saving code was completely non-reentrant,
       since it saved the registers to a global, static variable.
      I moved the storage for this onto the stack.
      A single binary built with this code was tested on an ARM11 (ARMv6)
       and a Cortex A8 (ARMv7 w/NEON), for both the encoder and decoder,
       and produced identical output, while using the correct accelerated
       functions on each.
      I did not test on any earlier processors.
      
      Change-Id: I45cbd63a614f4554c3b325c45d46c0806f009eaa
      b71962fd
  8. 22 Oct, 2010 1 commit
    • Timothy B. Terriberry's avatar
      Convert [4][4] matrices to [16] arrays. · 8f75ea6b
      Timothy B. Terriberry authored
      Most of the code that actually uses these matrices indexes them as
       if they were a single contiguous array, and coverity produces
       reports about the resulting accesses that overflow the static
       bounds of the first row.
      This is perfectly legal in C, but converting them to actual [16]
       arrays should eliminate the report, and removes a good deal of
       extraneous indexing and address operators from the code.
      
      Change-Id: Ibda479e2232b3e51f9edf3b355b8640520fdbf23
      8f75ea6b
  9. 18 Oct, 2010 1 commit
    • Johann's avatar
      copy compiler warning fixes · ce1ce992
      Johann authored
      generic version got fixed, but not the arm version. fixes:
      vp8/encoder/arm/mcomp_arm.c: In function 'vp8_full_search_sadx3':
      vp8/encoder/arm/mcomp_arm.c:1208: warning: pointer targets in passing
      argument 5 of 'fn_ptr->sdx3f' differ in signedness
      vp8/encoder/arm/mcomp_arm.c:1208: note: expected 'unsigned int *' but
      argument is of type 'int *'
      
      and another unsigned change to keep the files similar
      
      Change-Id: I1b6255dc3a03b90394a791ee0d15d8167d9454db
      ce1ce992
  10. 15 Oct, 2010 1 commit
    • Johann's avatar
      remove dead code · 963bcd6c
      Johann authored
      vp8_diamond_search_sadx4 isn't used in arm because there is no
      corrosponding sdx4df as in x86. rather than keep it in sync with
      ../mcomp.c, delete it
      
      vp8_hex_search had the original, more readable/understandable code if`d
      out. it's also available in ../mcomp.c, so remove the dead copy
      
      Change-Id: Ia42aa6e23b3a2e88040f467280befec091ec080e
      963bcd6c
  11. 09 Sep, 2010 1 commit
  12. 27 Jul, 2010 1 commit
    • John Koleszar's avatar
      neon: disable asm quantizer · d8009c07
      John Koleszar authored
      The assembly version of the quantizer has not been updated to match
      the new exact quantizer introduced in commit e04e2935. That commit tried
      to disable this code but missed the non-RTCD case.
      
      Thanks to David Baker <david.baker at openmarket.com> for isolating the
      issue and testing this fix.
      
      Change-Id: I0e51492dc6f8e44d2c10b587427448bf94135c65
      d8009c07
  13. 23 Jul, 2010 1 commit
    • Timothy B. Terriberry's avatar
      Make the quantizer exact. · e04e2935
      Timothy B. Terriberry authored
      This replaces the approximate division-by-multiplication in the
       quantizer with an exact one that costs just one add and one
       shift extra.
      The asm versions have not been updated in this patch, and thus
       have been disabled, since the new method requires different
       multipliers which are not compatible with the old method.
      
      Change-Id: I53ac887af0f969d906e464c88b1f4be69c6b1206
      e04e2935
  14. 18 Jun, 2010 1 commit
    • John Koleszar's avatar
      cosmetics: trim trailing whitespace · 94c52e4d
      John Koleszar authored
      When the license headers were updated, they accidentally contained
      trailing whitespace, so unfortunately we have to touch all the files
      again.
      
      Change-Id: I236c05fade06589e417179c0444cb39b09e4200d
      94c52e4d
  15. 04 Jun, 2010 1 commit
  16. 18 May, 2010 1 commit