1. 13 Jan, 2014 6 commits
  2. 11 Jan, 2014 8 commits
  3. 10 Jan, 2014 18 commits
  4. 09 Jan, 2014 8 commits
    • Johann's avatar
      Merge "Use the correct member for initialization" · e8192cf6
      Johann authored
      e8192cf6
    • Yaowu Xu's avatar
      Merge "Simplify set_rt_speed_feature()" · b1d81e19
      Yaowu Xu authored
      b1d81e19
    • Marco Paniconi's avatar
      Keep buffer clipped to maximum in change_config. · 193fa5c8
      Marco Paniconi authored
      Under a configuration change, where the bitrate suddenly decreases,
      the buffer level may be larger than maximum allowed (for that first frame to be encoded after change_config).
      This change keeps it clipped to its maximum level.
      
      Change-Id: I4d0b5b3d1fd8148600dd39e02bd630c9464baba5
      193fa5c8
    • Dmitry Kovalev's avatar
      c8e8d3a4
    • Yaowu Xu's avatar
      Simplify set_rt_speed_feature() · 2d381d76
      Yaowu Xu authored
      1. Made speed choices to be progressive
      2. Adjusted rt speed settings to achieve better speed/quality
      
      Overall, rt-5 gained 2.5% in compression/quality, encoding time of 720p
      niklas clip goes from 137,052ms to 121,874ms
      
      Change-Id: Ia6e7e1e15225395a868a2f1059c3db8e266e1600
      2d381d76
    • Jingning Han's avatar
      Optimze inv 16x16 DCT with 10 non-zero coeffs - P2 · af31b27a
      Jingning Han authored
      This commit further optimizes SSE2 operations in the second 1-D
      inverse 16x16 DCT, with (<10) non-zero coefficients. The average
      runtime of this module goes down from 779 cycles -> 725 cycles.
      
      Change-Id: Iac31b123640d9b1e8f906e770702936b71f0ba7f
      af31b27a
    • Yunqing Wang's avatar
      Merge "SSSE3 convolution optimization" · f3b9b97c
      Yunqing Wang authored
      f3b9b97c
    • levytamar82's avatar
      SSSE3 convolution optimization · 511d218c
      levytamar82 authored
      Optimizing all SSSE3 assembly for convolution:
      1. vp9_filter_block1d4_h8_sse2
      2. vp9_filter_block1d8_h8_sse2
      3. vp9_filter_block1d16_h8_sse2
      4. vp9_filter_block1d4_v8_sse2
      5. vp9_filter_block1d8_v8_sse2
      6. vp9_filter_block1d16_v8_sse2
      my optimization include:
      -processing 2x8 elements in one 128 bit register instead of processing
      8 elements in one 128 bit register.
      -removing unecessary loads.
      This optimization gives between 2.4% user level gain for 480p input
      and 1.6% user level gain for 720p.
      This Optimization done only for 64bit.
      
      Change-Id: Icb586dc0c938b56699864fcee6c52fd43b36b969
      511d218c