1. 05 Dec, 2017 7 commits
    • Johann's avatar
      remove spurious END · 8a2c5cb8
      Johann authored
      arm finishes assembly files with END but x86 does not.
      Cleans warning when building with nasm:
      warning: label alone on a line without a colon might be in error
      Change-Id: I048ef08f5183356bc0f44d0464110b284dd754b9
    • Sebastien Alaiwan's avatar
      Remove TPL_MV experiment · b0e7c1a2
      Sebastien Alaiwan authored
      This experiment has been abandonned for AV1.
      Change-Id: Ief159fa7cf41dafa1e71b140f585cbc5a7d0a67d
    • Jingning Han's avatar
      Simplify ref_mvs assignment · c3ef32a4
      Jingning Han authored
      Drop unnecessary ref_mvs assignment steps in the rate-distortion
      optimization process.
      Change-Id: Icbd0436d2f962ec6b1141b889cf5892b863f081d
    • Jingning Han's avatar
      Re-design drl index coding to remove ctx parsing dep · b56b71ae
      Jingning Han authored
      Re-design the dynamic motion vector index coding system to remove
      the context parsing dependency on the reconstructed motion vectors.
      Change-Id: I01dd6eda239a0bed32d8dc98f0f10f18249a76d4
    • Jingning Han's avatar
      Extend div_mult from 32 to 64 · d3c04cdd
      Jingning Han authored
      Change-Id: If7086930520d740d2610adeb699b68cdafab3ed3
    • Sebastien Alaiwan's avatar
      Cosmetics · c6d4eb10
      Sebastien Alaiwan authored
      Change-Id: I3923c7e8a41c33dfdb6c3b6f584abe8ab636ed5a
    • Sebastien Alaiwan's avatar
      Remove ANS experiment · b0460fa9
      Sebastien Alaiwan authored
      This experiment has been abandonned for AV1.
      Change-Id: I8110720cef1b56dbce4008a998d8f4281dd2fe44
  2. 04 Dec, 2017 20 commits
    • Debargha Mukherjee's avatar
      Support 64x16 and 16x64 rect intra transform sizes · b756d247
      Debargha Mukherjee authored
      Change-Id: I701f3a279c5b0f64df10b9c5daae8dd10498080b
    • Luc Trudeau's avatar
      Intra Prediction for 8x32 and 32x8 · d6d6a1d1
      Luc Trudeau authored
      Change-Id: I5c232b6948b236136aed609532d4cdf4a7016e4d
    • Luc Trudeau's avatar
      Intra Prediction for 4x16 and 16x4 · dd1acdfc
      Luc Trudeau authored
      Change-Id: Ia190c8b70173b48c91ae0dbb12d007c2a3f5d9b9
    • Debargha Mukherjee's avatar
      Fixes to make 4:1 rectangular intra work correctly · d2cfbefb
      Debargha Mukherjee authored
      This patch fixes and enables rectangular intra transform
      sizes for 4:1 partitions (that were turned off before).
      4:1 partitions can now use rectangular intra predictions with
      2:1 rectangular transform sizes.
      BDRATE lowres (single keyframe): -0.612%
      Change-Id: I6f062f7c08aae8eeb0a55d31e792c8f7e3f302a2
    • Timothy B. Terriberry's avatar
      daala_tx: Add SIMD versions of 4-point identity TX · f03f543d
      Timothy B. Terriberry authored
      These don't share the same kernel functions as the others so we can
      avoid doing two transposes for the rows and because we don't need
      to split short rows into multiple registers for the columns.
      The resulting IDTX implementations can be re-used for all sizes,
      though we might benefit from the larger AVX registers for the
      larger sizes.
      It might also be worth having a fast path for IDTX_IDTX to avoid an
      extra round-trip through memory, but that can be added in a
      separate patch if it proves worthwhile.
      Change-Id: I36fa4ea44c7dd2c165bff750d9bc8a213783041f
    • Timothy B. Terriberry's avatar
      daala_tx: Add SIMD versions of 4-point DST/FlipDST · 47f74646
      Timothy B. Terriberry authored
      Despite the function pointers used to avoid copying and pasting the
      boilerplate code around each transform kernel, the compiler will
      inline everything to straightline code, with all SIMD parameters
      kept in registers.
      Change-Id: I3a89d6499e1972967dcccf397507676ee57ee33b
    • Timothy B. Terriberry's avatar
      daala_tx: Remove +1/-1 butterflies from 4-point tx · 3f5bbc5e
      Timothy B. Terriberry authored
      This fixes a potential overflow when using the 4-point Type VII DST
      as the row transform in a 4x16 transform block.
      Results on subset1:
        PSNR | PSNR HVS |   SSIM | MS SSIM | CIEDE 2000
      0.0113 |   0.0367 | 0.0063 |  0.0013 |     0.0182
      Change-Id: Ib8ca6a2e06cd7d1b625cbbadcded2488eececd9c
    • Timothy B. Terriberry's avatar
      daala_tx: Add SIMD version of the 4-point DCT · 2e90b44e
      Timothy B. Terriberry authored
      Currently this only requires SSSE3 operations, but we build it as
      AVX2 to get support for 3-operand instructions. Separate versions
      for different instruction sets will be added later.
      Change-Id: Ib02c1496832923ecf6dccc1a208dc5ac5559dad2
    • Timothy B. Terriberry's avatar
      daala_tx: Add SIMD verification code · 1b65571b
      Timothy B. Terriberry authored
      This calls the C version of the transforms and verifies that the
      SIMD is a bit-exact match on every invocation. It must be manually
      enabled by editing the code to define DAALA_TX_VERIFY_SIMD. This is
      intended to be replaced by real unit tests in the future.
      Change-Id: I2c09c8a476cce21a9f48f9d7120185bfa7af42aa
    • Timothy B. Terriberry's avatar
      daala_tx: Add inverse TX SIMD dispatch · 18c803fa
      Timothy B. Terriberry authored
      This just adds a top-level daala_inv_txfm_add_avx2(), but no actual
      SIMD functions yet. It dispatches back to the C version for all TX
      types and sizes for the moment.
      Change-Id: I7a578a4af363f989615d01ea67ce031d8ceff977
    • Jingning Han's avatar
      Add the speed feature structure for codec dev · b49c6aea
      Jingning Han authored
      This commit re-structures the speed feature setup for the codec
      development purpose. Instead of progressively reducing encoder
      complexity at the expense of incremental coding loss, we allow a
      separate set of speed features, each corresponds to a certain
      category of coding units:
      1 << 0: transform coding
      1 << 1: inter prediction
      1 << 2: intra prediction
      1 << 3: block partition
      1 << 4: loop filters
      1 << 5: rd early skip
      [6 - 7] are left open for next adjustment.
      It is constructed to facilitate the codec development purpose.
      When working on a coding functions, one could choose to turn on
      one or more less related coding units to speed up the evaluation
      process. For example, to test a transform related experiment, one
      could set
      --dev-sf=2, 6, or 22
      which corresponds to turning on:
      2 - inter prediction speed features,
      6 - both inter / intra speed features,
      22 - inter / intra, and loop filter features.
      The goal is to allow faster experimental verification during the
      development process. With the experiment in a stable state, we
      can evaluate its performance in speed 0 at higher confidence level.
      Change-Id: Ib46c7dea2d2a60204c399dc01f10262c976adf0d
    • Imdad Sardharwalla's avatar
      Added monochrome option to the decoder. · 730c8054
      Imdad Sardharwalla authored
      When this is set (use --monochrome), all decoded frames
      will be given constant chroma planes.
      If the rawvideo option is used in conjunction with the
      monochrome option (i.e. --monochrome --rawvideo), the
      written output will only consist of the Y (luma) plane.
      Change-Id: I967817f1c3ebb1162fa9771b51cf6431120b835c
    • Jingning Han's avatar
      Remove inter mode context dependency on mvs · 835a49ec
      Jingning Han authored
      This commit resolves the inter mode context model dependency on
      the reconstructed motion vectors.
      Change-Id: I3fd885dba6c10be8b1dcd072c1a5b3925ef4d1f5
    • Dake He's avatar
      [lv_map_multi] simplify update_cdf · b79f1b67
      Dake He authored
      remove tmp0 in update_cdf due to the use of EC_MIN_PROB introduced by
      Thomas Davies.
      further changes to update_cdf include:
      1. Start the rate at 3+get_msb(nsymbs) and increase the rate by one at
      counts 16 and 32.
      2. Check if tmp is less than cdf[i] to avoid shifting a negative number.
      Change-Id: I5088ebd450d6e57ec6c3e92bb2f47a078489b947
    • Jingning Han's avatar
      Fix txb_skip context model · 4ca633dc
      Jingning Han authored
      Change-Id: I2ad279d27fb34c9c6bcee6029a40377541f066a7
    • Angie Chiang's avatar
      Set up txb size properly for TX64X64 · a9ba58ec
      Angie Chiang authored
      TX64X64 uses 32x32 coeff buffer
      Change-Id: Ied4279807207176d590af4c1fc4bb648a618d158
    • Angie Chiang's avatar
      Check if tx_type is valid in av1_get_tx_type() · 2ac1868b
      Angie Chiang authored
      Change-Id: I717bcec45e061e9685c00282f1c2a4d53a3481ef
    • Angie Chiang's avatar
      Use macro to set txk_type · bce07f1c
      Angie Chiang authored
      This will make txk_sel support maximum bsize to 128x128
      Change-Id: I33941966cb1ae4406ac68a2124c859c833a084d8
    • Zoe Liu's avatar
      Parse skip mode stats from aom_entropy_optimizer · 8c7bd928
      Zoe Liu authored
      Change-Id: I72a01937abc3ad5a1ddd5f5ef1ea79e2320343ad
    • Nathan E. Egge's avatar
      [daala_tx] Add new flattened 8-point Type-IV DST. · 9ad3343c
      Nathan E. Egge authored
      This 8-point Type-IV DST uses the same computation graph as the
       asymmetric 8-point Type-IV DST with the following changes:
        - The fDST and iDST contain different multiplication constants
        - The fDST does not reuse the passed shifts in the first additions
        - The iDST does not have any OD_RSHIFT1(t_) on the last additions
      This reused computation structure could be later pulled into a macro or
       exploited by a hardware implementation.
      Change-Id: Iac09c29549ce5dcf7752f71e9e6d24609e7b018a
  3. 03 Dec, 2017 4 commits
  4. 02 Dec, 2017 9 commits