- 20 Feb, 2018 6 commits
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David Barker authored
The compiler was complaining about the 'bd' parameter being unused in two functions. Change-Id: Iac2aa86234bb9554bb2dfa6ee6628bd1d09bfb1e
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Cheng Chen authored
Change _mm_srl_epi32 to _mm_sra_epi32. The difference is keeping sign bits in shifting. Otherwise there are mismatchings between simd and c functions, caught by unit tests. The other change is fix a typo. Change-Id: I18a9e9e12a661d181e9e904ffc64d802d624a36d
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Yaowu Xu authored
BUG=aomedia:1404 Change-Id: Ie52ef049a33a47915869a424f2ca73d706d8e5d0
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Yaowu Xu authored
The experiment is now fully adopted. Change-Id: I09960ed25defae98d1c3e5ee8bc93691f79677ec
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Yaowu Xu authored
This fixes a build warning. Change-Id: I1a7ca22e2a793c873df17d2335e964f4a82f7ea1
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Zoe Liu authored
Change-Id: Ia5ab13d7219ae79e685c999692a9f8bc35f0d360
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- 19 Feb, 2018 14 commits
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Yaowu Xu authored
This is to reduce the size of static tables. BUG=aomedia:1030 Change-Id: Id9a00352560af38eb381f403510ec3f3d7f1c29a
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Hui Su authored
Allow the CDF update to operate in different modes, e.g. update vs no update. The update mode is transmitted in the uncompressed frame header of every keyframe and intra-only frame. This patch only adds bitstream signaling and API support. The implementation of the update modes will be in later patches. Change-Id: Ic9fcd60e8a75f9c01f414253823d78cf9b3113dd
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Luc Trudeau authored
In av1_iht8x4_32_add_sse2, iidtx8 was using uninitialized values for rows 4,5,6,7. Change-Id: I12b41cedde6cdcc4c153a375571853a10d26c2df
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Jonathan Matthews authored
This is correct in the spec, but the code wasn't doing the check. BUG=aomedia:1405 Change-Id: I6e22f78d724583ad4cfdbbffc15e61b636810f76
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Hui Su authored
Change-Id: I19c49e5a5f0df0d767f156dcf006e5bf105bf6a0
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Jonathan Matthews authored
Introduced in Change-Id: I773f7ec9202d17c57bba44a698350e05101fa871 Change-Id: I147cce7c02db7144d8687855885910dbf8d9ab29
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Hui Su authored
Fixes the mismatches reported in the issue tracker. BUG=aomedia:1328 Change-Id: If60ef1c6cb5c28e21a6d6e71379fe1cb46ab6f0a
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Maxym Dmytrychenko authored
covers horizontal and vertical variations and including low and high bitdepth types. Appropriate tests are enabled Performance changes, SSE2 over C: Horizontal methods: up to 3x Vertical methods: up to 2x Change-Id: If430a916394c7befa743e4fbaa9913fd37c535ed
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Deepa K G authored
Make the av1_convolve_x_sr_sse2/avx2 support various bit shift options. Addition of asserts in the convolve functions. Change-Id: Ib6d1ada6c00a20e6e498af2672bd0bb76040d7d0
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Debargha Mukherjee authored
Fixes several failing 12-bit tests. Change-Id: If6da50bbd595adb270cb11820df97b34a22d7b82
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Andrey Norkin authored
BUG=aomedia:1400 Change-Id: I9cf4f0de4fb15295e4acbd8b511d93abd7897165
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Yaowu Xu authored
This aligns with the intention of data size, reduces stack size. Change-Id: Ib772143c20c860c871a1e4399f4a3d1024499680
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Yaowu Xu authored
The shift is as large as 49, which does not fit in 32 bit. Change-Id: Ic84e4eacfde7be386cbff411391366e0559a2824
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Yaowu Xu authored
Change-Id: I1b74c2efcef553f7d9a5a4a701ff29fa905a61f5
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- 18 Feb, 2018 6 commits
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Jingning Han authored
Tested in the low latency setting. Comparing the three options: (1). Cut off temporal mv altogether. (2). Use collocated mv referncing. (3). Use mfmv referencing. The current baseline is using (1). The results are: (2) improves the compression performance over (1) by -0.59% for lowres and -0.65% for midres. (3) improves over (1) by -1.05% for lowres and -1.43% for midres BUG=aomedia:1403 Change-Id: Ie683110ecbe16131f8aea123bca490f8897ebdd8
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Yaowu Xu authored
This avoid warnings of double->int conversion. Change-Id: I61ed7675354dfe4292511409dd56c534c2b48914
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Yunqing Wang authored
The restoration buffers are freed and allocated at every frame, which is not necessary. This patch makes the allocation to happen only when it is necessary. Change-Id: I773f7ec9202d17c57bba44a698350e05101fa871
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Debargha Mukherjee authored
The HIGHPRECISION_INTBUF=1 enables round_0 to be 3. This is now merged into the LOWPRECISION_BLEND flags for ease of management. Change-Id: Ia336f24ea87d824d7034012cfed9c4c3129bf6eb
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Debargha Mukherjee authored
By default turn: CONFIG_LOWPRECISION_BLEND=2 CONFIG_HIGHPRECISION_INTBUF=1 This is the adopted configuration from the codec WG. Change-Id: Ic8a324a4bf6316753bea07a17160ab93afacca3b
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Debargha Mukherjee authored
The compound tests are not needed for the Sr convolve functions, and are broken with LOWPRECISION_BLEND. Change-Id: I426bf872e70fc013cbd38f2bf0585aa920f8debd
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- 17 Feb, 2018 8 commits
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Zoe Liu authored
The CL makes the context design for single reference frame coding the same as that for the compound reference frame coding. There are 3 contexts designed for each of the binary symbols for the single reference frame scenario, and the designed contexts simply rely on the counts of the references used in the neighboring two blocks. Once this CL is merged, the coding of the reference frames, regardless of single prediction or compound prediction, will all follow the same context design pattern for all the binary symbols. The design logic is much simpler and the lines of code for each binary symbol context identification are reduced by 80%. Further, this CL has obtained a small coding gain for 30 frames with the default coding tools: lowres: avg_psnr -0.015%; ovr_psnr -0.021%; ssim -0.002% midres: avg_psnr -0.108%; ovr_psnr -0.139%; ssim -0.135% BUG=aomedia:1402 BUG=aomedia:973 Change-Id: Ia72a1d18e85ac3a05308675b60b95f80f2219c46
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Debargha Mukherjee authored
This addesses a crash in a situation where the scaled convolve function is called without a valid dst buffer in the conv_params structure. Change-Id: Ia4a0a1213f06447155d6c92aa9efc183d8c4a79c
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Zoe Liu authored
This flag enables an extra bit in the frame header to indicate the signaling choice of the reference frames in the frame header. Change-Id: I67ef0cbb0673bf877189236b5060f2a854a05d11
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Jingning Han authored
Change-Id: I24e98062fec2cf73e294d34bf02419f7917a9bf0
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Jingning Han authored
Fix the rate cost count when the optimize_b route is set off in the rate-distortion optimization process. Thanks to pohhsu@microsoft for finding this issue and pointing the fix. Change-Id: I54d9ec8102792a1575fc66bc6be2003e94eeb488
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Jingning Han authored
When a coding block runs VERT_A partition, the coding order does not follow raster order. This requires a special handle on the bottom left square block to disable its reference towards the top-right corner. Prior to this change the codebase would disable the bottom-right square, as well as the right rectangular blocks, from referencing the top-right mv. This commit fixes such check condition to allow the right rectangular block to access the top right mv. BUG=aomedia:1343 Change-Id: I87049f0cec8ed7557a87c3fdef83e01498bbcd75
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Jingning Han authored
Remove deprecated context models for drl index coding. BUG=aomedia:1208 Change-Id: If255fa93d0c746738f0fc005464388e790c89b63
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Urvang Joshi authored
Change-Id: I40b7672ed98f2d1a49a7a9aabfd313ba64b3e8fb
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- 16 Feb, 2018 6 commits
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Johann authored
The 4x2 transforms gives a compile warning with gcc 6.3.0 but appears to be unused: *((void *)&temp2+8)' is used uninitialized in this function Change-Id: I8b08e05d0365dc117b5374ec00bddc6f7bd84bd3
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Tom Finegan authored
Also some minor cosmetic changes and style fixes. BUG=aomedia:1125 Change-Id: Ide24057736376accd2f9907ef87b5a725ab3f3c2
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Angie Chiang authored
Change-Id: I103547d5bd4c9537cc0640a10d50f5c3cb6b7771
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Jingning Han authored
Make the convolve_2d_sr_avx2 to support various bit shift options. Turn back on the SIMD functions for av1_convolve_2d_sr. Change-Id: I38b29eee40831c8c88e574884205bc0fdf886916
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Jingning Han authored
Make the convolve_2d_sr_sse2 support all the bit shift tuning settings in CONFIG_LOWPRECISION_BLEND and off. Change-Id: I497105d9d7f0a0f9c5edcac55b366825ec13a2ed
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Angie Chiang authored
Let the cdf update order match the actual coding order Change-Id: Iaac0830b2530228ce1a4ea95d842c573dd3d0684
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