1. 25 Oct, 2010 1 commit
    • Timothy B. Terriberry's avatar
      Add runtime CPU detection support for ARM. · b71962fd
      Timothy B. Terriberry authored
      The primary goal is to allow a binary to be built which supports
       NEON, but can fall back to non-NEON routines, since some Android
       devices do not have NEON, even if they are otherwise ARMv7 (e.g.,
       Tegra).
      The configure-generated flags HAVE_ARMV7, etc., are used to decide
       which versions of each function to build, and when
       CONFIG_RUNTIME_CPU_DETECT is enabled, the correct version is chosen
       at run time.
      In order for this to work, the CFLAGS must be set to something
       appropriate (e.g., without -mfpu=neon for ARMv7, and with
       appropriate -march and -mcpu for even earlier configurations), or
       the native C code will not be able to run.
      The ASFLAGS must remain set for the most advanced instruction set
       required at build time, since the ARM assembler will refuse to emit
       them otherwise.
      I have not attempted to make any changes to configure to do this
       automatically.
      Doing so will probably require the addition of new configure options.
      
      Many of the hooks for RTCD on ARM were already there, but a lot of
       the code had bit-rotted, and a good deal of the ARM-specific code
       is not integrated into the RTCD structs at all.
      I did not try to resolve the latter, merely to add the minimal amount
       of protection around them to allow RTCD to work.
      Those functions that were called based on an ifdef at the calling
       site were expanded to check the RTCD flags at that site, but they
       should be added to an RTCD struct somewhere in the future.
      The functions invoked with global function pointers still are, but
       these should be moved into an RTCD struct for thread safety (I
       believe every platform currently supported has atomic pointer
       stores, but this is not guaranteed).
      
      The encoder's boolhuff functions did not even have _c and armv7
       suffixes, and the correct version was resolved at link time.
      The token packing functions did have appropriate suffixes, but the
       version was selected with a define, with no associated RTCD struct.
      However, for both of these, the only armv7 instruction they actually
       used was rbit, and this was completely superfluous, so I reworked
       them to avoid it.
      The only non-ARMv4 instruction remaining in them is clz, which is
       ARMv5 (not even ARMv5TE is required).
      Considering that there are no ARM-specific configs which are not at
       least ARMv5TE, I did not try to detect these at runtime, and simply
       enable them for ARMv5 and above.
      
      Finally, the NEON register saving code was completely non-reentrant,
       since it saved the registers to a global, static variable.
      I moved the storage for this onto the stack.
      A single binary built with this code was tested on an ARM11 (ARMv6)
       and a Cortex A8 (ARMv7 w/NEON), for both the encoder and decoder,
       and produced identical output, while using the correct accelerated
       functions on each.
      I did not test on any earlier processors.
      
      Change-Id: I45cbd63a614f4554c3b325c45d46c0806f009eaa
      b71962fd
  2. 09 Sep, 2010 1 commit
  3. 23 Aug, 2010 1 commit
    • Fritz Koenig's avatar
      Rework idct calling structure. · 93c32a55
      Fritz Koenig authored
      Moving the eob structure allows for a non-struct based
      function to handle decoding an entire mb of
      idct/dequant/recon data.  This allows for SIMD functions
      to idct/dequant/recon multiple blocks at once.
      
      SSE2 implementation gives 3% gain on Atom.
      
      Change-Id: I8a8f3efd546ea4e0535f517d94f347cfb737c9c2
      93c32a55
  4. 26 Jul, 2010 1 commit
    • Johann's avatar
      update arm idct functions · 56f5a9a0
      Johann authored
      Jeff Muizelaar posted some changes to the idct/reconstruction c code.
      This is the equivalent update for the arm assembly.
      
      This shows a good boost on v6, and a minor boost on neon.
      Here are some numbers for highway in qcif, 2641 frames:
      HEAD neon: ~161 fps
      new neon:  ~162 fps
      HEAD v6:   ~102 fps
      new v6:    ~106 fps
      
      The following functions have been updated for armv6 and neon:
      vp8_dc_only_idct_add
      vp8_dequant_idct_add
      vp8_dequant_dc_idct_add
      
      Conflicts:
      
      	vp8/decoder/arm/armv6/dequantdcidct_v6.asm
      	vp8/decoder/arm/armv6/dequantidct_v6.asm
      
      Resolved by removing these files. When I rewrote the functions, I also
      moved the files to dequant_dc_idct_v6.asm/dequant_idct_v6.asm
      
      Change-Id: Ie3300df824d52474eca1a5134cf22d8b7809a5d4
      56f5a9a0
  5. 23 Jul, 2010 1 commit
    • Jeff Muizelaar's avatar
      Combine idct and reconstruction steps · b2fa74ac
      Jeff Muizelaar authored
      This moves the prediction step before the idct and combines the idct and
      reconstruction steps into a single step. Combining them seems to give an
      overall decoder performance improvement of about 1%.
      
      Change-Id: I90d8b167ec70d79c7ba2ee484106a78b3d16e318
      b2fa74ac
  6. 18 Jun, 2010 1 commit
    • John Koleszar's avatar
      cosmetics: trim trailing whitespace · 94c52e4d
      John Koleszar authored
      When the license headers were updated, they accidentally contained
      trailing whitespace, so unfortunately we have to touch all the files
      again.
      
      Change-Id: I236c05fade06589e417179c0444cb39b09e4200d
      94c52e4d
  7. 16 Jun, 2010 1 commit
    • Timothy B. Terriberry's avatar
      Change bitreader to use a larger window. · c17b62e1
      Timothy B. Terriberry authored
      Change bitreading functions to use a larger window which is refilled less
       often.
      
      This makes it cheap enough to do bounds checking each time the window is
       refilled, which avoids the need to copy the input into a large circular
       buffer.
      This uses less memory and speeds up the total decode time by 1.6% on an ARM11,
       2.8% on a Cortex A8, and 2.2% on x86-32, but less than 1% on x86-64.
      
      Inlining vp8dx_bool_decoder_fill() has a big penalty on x86-32, as does moving
       the refill loop to the front of vp8dx_decode_bool().
      However, having the refill loop between computation of the split values and
       the branch in vp8_decode_mb_tokens() is a big win on ARM (presumably due to
       memory latency and code size: refilling after normalization duplicates the
       code in the DECODE_AND_BRANCH_IF_ZERO and DECODE_AND_LOOP_IF_ZERO cases.
      Unfortunately, refilling at the end of vp8dx_bool_decoder_fill() and at the
       beginning of each decode step in vp8_decode_mb_tokens() means the latter
       requires an extra refill at the end.
      Platform-specific versions could avoid the problem, but would require most of
       detokenize.c to be duplicated.
      
      Change-Id: I16c782a63376f2a15b78f8086d899b987204c1c7
      c17b62e1
  8. 04 Jun, 2010 1 commit
  9. 18 May, 2010 1 commit