1. 09 Nov, 2017 10 commits
    • Rostislav Pehlivanov's avatar
      Add the q_segmentation experiment · f624dd5a
      Rostislav Pehlivanov authored
      This experiment implements low-cost delta q signalling on a per-block basis
      for all non-inter frame types, which would allow for more efficient AQ
      which bases its decisions on temporal information.
      
      Based on an Intel proposal from March.
      
      Change-Id: I18e73d8b12f4caa0b165df12c58ab506271bec03
      f624dd5a
    • Sebastien Alaiwan's avatar
      Remove LGT experiment · 2fa189e5
      Sebastien Alaiwan authored
      This experiment has been abandonned for AV1.
      
      Change-Id: If560a67d00b8ae3daa377a59293d5125a8cb7902
      2fa189e5
    • Jingning Han's avatar
      Remove unnecessary handle_inter_mode call · 5d0320f7
      Jingning Han authored
      Remove the redundant handle_inter_mode calls from the jnt-comp
      encoding route.
      
      Change-Id: I1f4fded525cfd3ead7d06c977ab8d99cb7f02273
      5d0320f7
    • Yaowu Xu's avatar
      Disable in-loop filtering for single_tile_decoding · 35ee2345
      Yaowu Xu authored
      BUG=aomedia:1014
      
      Change-Id: I8846432861e9859a00f702407a82d4223c093fe2
      35ee2345
    • Debargha Mukherjee's avatar
      Reorder ext_comp_ref modes · c1077e9c
      Debargha Mukherjee authored
      Change-Id: Ie392e88609554fea99e74c94812799f72b78725b
      c1077e9c
    • Monty Montgomery's avatar
      Add Daala TX to rectangular 32x64 and 64x32 transforms · 6a2a75b6
      Monty Montgomery authored
      This patch adds Daala TX transforms ot the 32x64 and 64x32 transform
      block sizes using Q3 (up 4, down 1) scaling.
      
      subset 1:
      monty-daalaTX-fulltest-Daalabaseline-s1@2017-11-07T00:01:46.582Z ->
       monty-daalaTX-LBD-Daala32x64-s1-Z@2017-11-07T06:10:58.523Z
      
        PSNR | PSNR Cb | PSNR Cr | PSNR HVS |   SSIM | MS SSIM | CIEDE 2000
      0.0112 | -0.0769 |  0.0799 |   0.0567 | 0.0099 | -0.0077 |    -0.0446
      
      objective 1 fast:
      monty-daalaTX-fulltest-Daalabaseline-o1f4@2017-11-07T05:59:16.553Z ->
       monty-daalaTX-LBD-Daala32x64-o1f4-Z@2017-11-07T06:10:11.519Z
      
         PSNR | PSNR Cb | PSNR Cr | PSNR HVS |    SSIM | MS SSIM | CIEDE 2000
      -0.0190 |  0.0926 | -0.0730 |  -0.0516 | -0.0037 | -0.0588 |     0.1310
      
      Change-Id: I6246ecba388ae81deadc7b306dc3404fa7869aab
      6a2a75b6
    • Monty Montgomery's avatar
      Separate quantizers used for quantization from RDO · 125c0fca
      Monty Montgomery authored
      Generalize quantizer setup so that quantization and TX can use
      different coefficient shifts/scalings without inpacting RDO lambda
      generation.
      
      This patch is documentaiton + a minor refactor setting up later
      work; it causes no functional change.
      
      monty-daalaTX-fulltest-Daalabaseline-o1f@2017-11-07T00:01:20.779Z ->
       monty-daalaTX-fulltest-DaalaRDO-o1f@2017-11-07T00:02:31.347Z
      
      PSNR | PSNR Cb | PSNR Cr | PSNR HVS | SSIM | MS SSIM | CIEDE 2000
       N/A |  0.0000 |  0.0000 |      N/A |  N/A |     N/A |        N/A
      (note-- the numbers above were collected using --cpu-used=3, which
       appears to be newly broken.)
      
      monty-daalaTX-fulltest-Daalabaseline-o1f4@2017-11-07T05:59:16.553Z ->
       monty-daalaTX-fulltest-DaalaRDO-o1f4@2017-11-07T05:59:50.180Z
      
        PSNR | PSNR Cb | PSNR Cr | PSNR HVS |   SSIM | MS SSIM | CIEDE 2000
      0.0000 |  0.0000 |  0.0000 |   0.0000 | 0.0000 |  0.0000 |     0.0000
      
      monty-daalaTX-fulltest-Daalabaseline-s1@2017-11-07T00:01:46.582Z ->
       monty-daalaTX-fulltest-DaalaRDO-s1@2017-11-07T00:02:56.282Z
      
        PSNR | PSNR Cb | PSNR Cr | PSNR HVS |   SSIM | MS SSIM | CIEDE 2000
      0.0000 |  0.0000 |  0.0000 |   0.0000 | 0.0000 |  0.0000 |     0.0000
      
      Change-Id: Ia5a3c052eacd17184ca1b0fe6d032cfb9afdb77f
      125c0fca
    • Linfeng Zhang's avatar
      Initialize update_eob to -1 in txb code · 848f7bc7
      Linfeng Zhang authored
      To skip possible unnecessary looping.
      
      Change-Id: If611d344ab39eee53de6c5256ce5f8febedecc9b
      848f7bc7
    • Zoe Liu's avatar
      Add one more level for selective ref frame speed feature · 451672e2
      Zoe Liu authored
      Change-Id: Idb4c986d8cd795e2d2ea76023674c8b2ba5d353c
      451672e2
    • Zoe Liu's avatar
      Align encoder stats update on delta_qindex and delta_lflevel · 59d2dd02
      Zoe Liu authored
      This patch is to add the according changes to update_stats() on the
      encoder side for signaling of delta_qindex and delta_lflevel, aligned
      with the following CL:
      https://aomedia-review.googlesource.com/c/aom/+/30801
      
      BUG=aomedia:992
      
      Change-Id: Ie627d4ebce085da85bcee7d5d3f9a7c358725481
      59d2dd02
  2. 08 Nov, 2017 14 commits
  3. 07 Nov, 2017 16 commits
    • Hui Su's avatar
      intrabc: control reference areas · 64463e74
      Hui Su authored
      Change-Id: I853a0e4b5fc7e7b5c1745b401214ef71b65aad60
      64463e74
    • Michael Bebenita's avatar
      Fix skip encoding in analyzer · 7a144cd6
      Michael Bebenita authored
      Change-Id: I26969ab591482dc9a6095059ba8a8935090f6e5e
      7a144cd6
    • Rupert Swarbrick's avatar
      Move loop restoration reset into a helper function · 76405206
      Rupert Swarbrick authored
      This seems a little cleaner than having the loop open coded in four
      places.
      
      Change-Id: I2ce7be2745ba3575f618d9e261ab767d10f551f7
      76405206
    • Rupert Swarbrick's avatar
      Remove duplicated code for reading/writing sequence header · b394bfec
      Rupert Swarbrick authored
      Teach read_sequence_header_obu and write_sequence_header_obu to just
      call read_sequence_header and write_sequence_header, respectively.
      
      Change-Id: Iff27b5cfbccab0ebaf2e28d72df3d6606964936f
      b394bfec
    • Rupert Swarbrick's avatar
      Fix widths in OBU reading code · 4cbf05c5
      Rupert Swarbrick authored
      It was mixing uint32_t and size_t, which isn't correct on a 64-bit
      system and causes compilation warnings.
      
      Change-Id: I3677c02cb366d60175e762ec4249d2445ee729de
      4cbf05c5
    • Rupert Swarbrick's avatar
      Use correct RestorationInfo when encoding tilesize · 4596deb2
      Rupert Swarbrick authored
      Also, factor out some long constants to avoid line wrapping.
      
      BUG=aomedia:1009
      
      Change-Id: I7850c27d22ef8b927c3554f1083bc7bdf2c7c6b3
      4596deb2
    • Sebastien Alaiwan's avatar
      Remove LPF_DIRECT experiment · 472b1744
      Sebastien Alaiwan authored
      This experiment has been abandonned for AV1.
      
      Change-Id: I599608060ade646d6551dea7cfc680f83ee9d507
      472b1744
    • Hui Su's avatar
      Don't use sub8x8_inter for intrabc blocks · 96e119a3
      Hui Su authored
      Change-Id: Ibaeea878e37f193e405910fac34176065cb5d2e3
      96e119a3
    • Hui Su's avatar
      intrabc: add assertions for DV subpel · 1e6bf6ba
      Hui Su authored
      DV and ref DV should not have subpel values.
      
      Change-Id: I7c47c442936f1d6bda36314812c44498ba6195a6
      1e6bf6ba
    • Hui Su's avatar
      intrabc: only consider intrabc blocks' mvs for ref mv · 1e68d5dd
      Hui Su authored
      When generating ref mv list, only consider neighbor blocks that use intrabc.
      
      Change-Id: I69f838a38478ce118f936dbf431048d3d42d4f34
      1e68d5dd
    • Linfeng Zhang's avatar
      Add levels array in av1_optimize_txb() · 1015a347
      Linfeng Zhang authored
      av1_txb_init_levels() has prefix 'av1' because it will be optimized
      and not static later.
      
      Change-Id: I988da817335f122522a76c4412207c3a6fdd6b71
      1015a347
    • Joe Young's avatar
      Enable ext-intra-mod by default · 2edfc37b
      Joe Young authored
      Provisionally adopted on 2017-10-31
      
      (Also an asan warning fix + few non-functional changes)
      
      Change-Id: I2ff4f34f8b20d2eeb567f2e5b1e57b296a97be82
      2edfc37b
    • Yaowu Xu's avatar
      Avoid left shift of negative numbers · 2a91ab7e
      Yaowu Xu authored
      Change-Id: I21f956a83687ebaeab81577aabdbfed2ea2b4dd2
      2a91ab7e
    • Zoe Liu's avatar
      Speed up ref selection by enforcing max 6 frames · f452fdfe
      Zoe Liu authored
      A speedup feature that enforces the maximum number of reference frames
      to evaluate for each arbitrary frame to be 6, as opposed to the maximum
      syntax-allowed number of reference frames which is 7, through the
      following rules:
      
      (1) When all the possible reference frames are availble, we reduce the
          number of reference frames (7) by 1 by removing one reference
          frame;
      (2) Always retain GOLDEN_FARME/ALTEF_FRAME;
      (3) Check the earliest 2 remaining reference frames, and there are two
          options to remove one reference frame:
          (a) Remove the one with the lower quality factor; Otherwise if
          both frames have been coded at the same quality level, remove the
          earliest reference frame;
          (b) Always remove the earliest reference frame.
          Currently set option (a).
      
      This patch has demonstrated an encoder speedup of ~8.5%. It is under
      speed2 with "selective_ref_frame >= 2". (May be considered to move
      to speed1 later once the coding performance impact is evaluated
      further.)
      
      Using the following configure setups, the coding performance has been
      dropped on Google test sets (50 frames) in BDRate by ~0.2% for lowres
      and by ~0.1% for midres:
      --enable-experimental --disable-convolve-round --disable-ext-partition
      --disable-ext-partition-types --disable-txk-sel --disable-txm
      
      Change-Id: I84317bae00bfd90b2c3d301858a849f441974e6f
      f452fdfe
    • Nathan E. Egge's avatar
      Replace OD_UNBIASED_RSHIFT32() with OD_RSHIFT1(). · 49fad89a
      Nathan E. Egge authored
      Because daala_tx only ever does an unbiased shift by 1, we can replace
       the varible shift macro with a simpler hardcoded implementation.
      This patch causes no change in behavior.
      
      subset-1:
      
      daala_tx@2017-11-04T07:20:17.571Z ->
       daala_tx-no_op@2017-11-04T07:21:06.231Z
      
        PSNR | PSNR Cb | PSNR Cr | PSNR HVS |   SSIM | MS SSIM | CIEDE 2000
      0.0000 |  0.0000 |  0.0000 |   0.0000 | 0.0000 |  0.0000 |     0.0000
      
      Change-Id: Ifddfef079320de0df09d9bc39757af9fe81e3c38
      49fad89a
    • Monty Montgomery's avatar
      Fix build for CONFIG_DAALA_TX and CONFIG_TX64X64 · 683f70e7
      Monty Montgomery authored
      The recent 64x32 and 32x64 patches break the build when
      CONFIG_DAALA_TX and CONFIG_TX64X64 are enabled simultaneously.  This
      is a minor correction that fixes the build problem.
      
      Change-Id: I53cd8df9160fc35b67f2ac16bddcfab08425cf8e
      683f70e7