Commit 9f001f35 authored by Sebastien Alaiwan's avatar Sebastien Alaiwan

Remove MRC_TX experiment

This experiment has been abandonned for AV1.

Change-Id: Ib9a8eea6b0ad5580dc81836be8fc5e898bb9bb45
parent 991dd22e
......@@ -1179,129 +1179,6 @@ void aom_idct32_c(const tran_low_t *input, tran_low_t *output) {
output[31] = WRAPLOW(step1[0] - step1[31]);
}
#if CONFIG_MRC_TX
void aom_imrc32x32_1_add_c(const tran_low_t *input, uint8_t *dest, int stride,
uint8_t *mask) {
int i, j;
tran_high_t a1;
tran_low_t out = WRAPLOW(dct_const_round_shift(input[0] * cospi_16_64));
out = WRAPLOW(dct_const_round_shift(out * cospi_16_64));
a1 = ROUND_POWER_OF_TWO(out, 6);
if (a1 == 0) return;
for (j = 0; j < 32; ++j) {
for (i = 0; i < 32; ++i) {
int mask_val = mask[i];
dest[i] = mask_val ? clip_pixel_add(dest[i], a1) : dest[i];
}
mask += 32;
dest += stride;
}
}
void aom_imrc32x32_1024_add_c(const tran_low_t *input, uint8_t *dest,
int stride, uint8_t *mask) {
tran_low_t out[32 * 32];
tran_low_t *outptr = out;
int i, j;
tran_low_t temp_in[32], temp_out[32];
// Rows
for (i = 0; i < 32; ++i) {
int16_t zero_coeff[16];
for (j = 0; j < 16; ++j) zero_coeff[j] = input[2 * j] | input[2 * j + 1];
for (j = 0; j < 8; ++j)
zero_coeff[j] = zero_coeff[2 * j] | zero_coeff[2 * j + 1];
for (j = 0; j < 4; ++j)
zero_coeff[j] = zero_coeff[2 * j] | zero_coeff[2 * j + 1];
for (j = 0; j < 2; ++j)
zero_coeff[j] = zero_coeff[2 * j] | zero_coeff[2 * j + 1];
if (zero_coeff[0] | zero_coeff[1])
aom_idct32_c(input, outptr);
else
memset(outptr, 0, sizeof(tran_low_t) * 32);
input += 32;
outptr += 32;
}
// Columns
for (i = 0; i < 32; ++i) {
for (j = 0; j < 32; ++j) temp_in[j] = out[j * 32 + i];
aom_idct32_c(temp_in, temp_out);
for (j = 0; j < 32; ++j) {
// Only add the coefficient if the mask value is 1
int mask_val = mask[j * 32 + i];
dest[j * stride + i] =
mask_val ? clip_pixel_add(dest[j * stride + i],
ROUND_POWER_OF_TWO(temp_out[j], 6))
: dest[j * stride + i];
}
}
}
void aom_imrc32x32_135_add_c(const tran_low_t *input, uint8_t *dest, int stride,
uint8_t *mask) {
tran_low_t out[32 * 32] = { 0 };
tran_low_t *outptr = out;
int i, j;
tran_low_t temp_in[32], temp_out[32];
// Rows
// only upper-left 16x16 has non-zero coeff
for (i = 0; i < 16; ++i) {
aom_idct32_c(input, outptr);
input += 32;
outptr += 32;
}
// Columns
for (i = 0; i < 32; ++i) {
for (j = 0; j < 32; ++j) temp_in[j] = out[j * 32 + i];
aom_idct32_c(temp_in, temp_out);
for (j = 0; j < 32; ++j) {
// Only add the coefficient if the mask value is 1
int mask_val = mask[j * 32 + i];
dest[j * stride + i] =
mask_val ? clip_pixel_add(dest[j * stride + i],
ROUND_POWER_OF_TWO(temp_out[j], 6))
: dest[j * stride + i];
}
}
}
void aom_imrc32x32_34_add_c(const tran_low_t *input, uint8_t *dest, int stride,
uint8_t *mask) {
tran_low_t out[32 * 32] = { 0 };
tran_low_t *outptr = out;
int i, j;
tran_low_t temp_in[32], temp_out[32];
// Rows
// only upper-left 8x8 has non-zero coeff
for (i = 0; i < 8; ++i) {
aom_idct32_c(input, outptr);
input += 32;
outptr += 32;
}
// Columns
for (i = 0; i < 32; ++i) {
for (j = 0; j < 32; ++j) temp_in[j] = out[j * 32 + i];
aom_idct32_c(temp_in, temp_out);
for (j = 0; j < 32; ++j) {
// Only add the coefficient if the mask value is 1
int mask_val = mask[j * 32 + i];
dest[j * stride + i] =
mask_val ? clip_pixel_add(dest[j * stride + i],
ROUND_POWER_OF_TWO(temp_out[j], 6))
: dest[j * stride + i];
}
}
}
#endif // CONFIG_MRC_TX
void aom_idct32x32_1024_add_c(const tran_low_t *input, uint8_t *dest,
int stride) {
tran_low_t out[32 * 32];
......
......@@ -53,21 +53,6 @@ static INLINE tran_high_t check_range(tran_high_t input, int bd) {
#define WRAPLOW(x) ((int32_t)check_range(x, 8))
#define HIGHBD_WRAPLOW(x, bd) ((int32_t)check_range((x), bd))
#if CONFIG_MRC_TX
// These each perform dct but add coefficients based on a mask
void aom_imrc32x32_1_add_c(const tran_low_t *input, uint8_t *dest, int stride,
uint8_t *mask);
void aom_imrc32x32_1024_add_c(const tran_low_t *input, uint8_t *dest,
int stride, uint8_t *mask);
void aom_imrc32x32_135_add_c(const tran_low_t *input, uint8_t *dest, int stride,
uint8_t *mask);
void aom_imrc32x32_34_add_c(const tran_low_t *input, uint8_t *dest, int stride,
uint8_t *mask);
#endif // CONFIG_MRC_TX
void aom_idct4_c(const tran_low_t *input, tran_low_t *output);
void aom_idct8_c(const tran_low_t *input, tran_low_t *output);
void aom_idct16_c(const tran_low_t *input, tran_low_t *output);
......
......@@ -32,17 +32,6 @@ typedef struct txfm_param {
// bd==8 implies !is_hbd, but that's not certain right now.
int is_hbd;
TxSetType tx_set_type;
#if CONFIG_MRC_TX
int is_inter;
#endif // CONFIG_MRC_TX
#if CONFIG_MRC_TX
int stride;
uint8_t *dst;
#if CONFIG_MRC_TX
int *valid_mask;
uint8_t *mask;
#endif // CONFIG_MRC_TX
#endif // CONFIG_MRC_TX
// for inverse transforms only
#if CONFIG_ADAPT_SCAN
const int16_t *eob_threshold;
......
......@@ -230,136 +230,11 @@ static INLINE TX_TYPE av1_rotate_tx_type(TX_TYPE tx_type) {
case H_ADST: return V_ADST;
case V_FLIPADST: return H_FLIPADST;
case H_FLIPADST: return V_FLIPADST;
#if CONFIG_MRC_TX
case MRC_DCT: return MRC_DCT;
#endif // CONFIG_MRC_TX
default: assert(0); return TX_TYPES;
}
}
#endif // CONFIG_TXMG
#if CONFIG_MRC_TX
static INLINE void sum1x5(uint16_t *input, uint16_t *output, int dim) {
memset(output, 0, sizeof(*output) * dim);
// Border padding
input[dim + 2] = input[dim + 3] = input[dim + 1];
input[0] = input[1] = input[2];
input += 2;
for (int i = 0; i < dim; i++)
for (int j = -2; j < 3; j++) output[i] += input[i + j];
}
// Smooths the residual over a 5x5 window and thresholds to produce a mask
static INLINE int get_mrc_diff_mask_inter(const int16_t *diff, int diff_stride,
uint8_t *mask, int mask_stride,
int width, int height) {
assert(SIGNAL_MRC_MASK_INTER);
int n_masked_vals = 0;
uint16_t tmp_out[MAX_SB_SIZE], tmp_in[MAX_SB_SIZE + 4], out[MAX_SB_SQUARE];
const uint16_t thresh = 10;
// Rows
for (int i = 0; i < height; ++i) {
for (int j = 0; j < width; ++j)
tmp_in[j + 2] = abs(diff[i * diff_stride + j]);
sum1x5(tmp_in, tmp_out, width);
for (int j = 0; j < width; ++j) {
out[i * MAX_SB_SIZE + j] = (uint16_t)DIVIDE_AND_ROUND(tmp_out[j], 5);
}
}
// Columns
for (int j = 0; j < width; ++j) {
for (int i = 0; i < height; ++i) tmp_in[i + 2] = out[i * MAX_SB_SIZE + j];
sum1x5(tmp_in, tmp_out, height);
for (int i = 0; i < height; ++i) {
mask[i * mask_stride + j] =
(uint8_t)DIVIDE_AND_ROUND(tmp_out[i], 5) > thresh;
n_masked_vals += mask[i * mask_stride + j];
}
}
return n_masked_vals;
}
static INLINE int get_mrc_pred_mask_inter(const uint8_t *pred, int pred_stride,
uint8_t *mask, int mask_stride,
int width, int height) {
// placeholder mask generation function
int n_masked_vals = 0;
for (int i = 0; i < height; ++i) {
for (int j = 0; j < width; ++j) {
mask[i * mask_stride + j] = pred[i * pred_stride + j] > 100 ? 1 : 0;
n_masked_vals += mask[i * mask_stride + j];
}
}
return n_masked_vals;
}
static INLINE int get_mrc_diff_mask_intra(const int16_t *diff, int diff_stride,
uint8_t *mask, int mask_stride,
int width, int height) {
// placeholder mask generation function
assert(SIGNAL_MRC_MASK_INTRA);
int n_masked_vals = 0;
for (int i = 0; i < height; ++i) {
for (int j = 0; j < width; ++j) {
mask[i * mask_stride + j] = diff[i * diff_stride + j] > 100 ? 1 : 0;
n_masked_vals += mask[i * mask_stride + j];
}
}
return n_masked_vals;
}
static INLINE int get_mrc_pred_mask_intra(const uint8_t *pred, int pred_stride,
uint8_t *mask, int mask_stride,
int width, int height) {
// placeholder mask generation function
int n_masked_vals = 0;
for (int i = 0; i < height; ++i) {
for (int j = 0; j < width; ++j) {
mask[i * mask_stride + j] = pred[i * pred_stride + j] > 100 ? 1 : 0;
n_masked_vals += mask[i * mask_stride + j];
}
}
return n_masked_vals;
}
static INLINE int get_mrc_diff_mask(const int16_t *diff, int diff_stride,
uint8_t *mask, int mask_stride, int width,
int height, int is_inter) {
if (is_inter) {
assert(USE_MRC_INTER && "MRC invalid for inter blocks");
assert(SIGNAL_MRC_MASK_INTER);
return get_mrc_diff_mask_inter(diff, diff_stride, mask, mask_stride, width,
height);
} else {
assert(USE_MRC_INTRA && "MRC invalid for intra blocks");
assert(SIGNAL_MRC_MASK_INTRA);
return get_mrc_diff_mask_intra(diff, diff_stride, mask, mask_stride, width,
height);
}
}
static INLINE int get_mrc_pred_mask(const uint8_t *pred, int pred_stride,
uint8_t *mask, int mask_stride, int width,
int height, int is_inter) {
if (is_inter) {
assert(USE_MRC_INTER && "MRC invalid for inter blocks");
return get_mrc_pred_mask_inter(pred, pred_stride, mask, mask_stride, width,
height);
} else {
assert(USE_MRC_INTRA && "MRC invalid for intra blocks");
return get_mrc_pred_mask_intra(pred, pred_stride, mask, mask_stride, width,
height);
}
}
static INLINE int is_valid_mrc_mask(int n_masked_vals, int width, int height) {
return !(n_masked_vals == 0 || n_masked_vals == (width * height));
}
#endif // CONFIG_MRC_TX
// Utility function that returns the log of the ratio of the col and row
// sizes.
static INLINE int get_rect_tx_log_ratio(int col, int row) {
......
......@@ -283,10 +283,6 @@ typedef struct MB_MODE_INFO {
#endif
int8_t seg_id_predicted; // valid only when temporal_update is enabled
#if CONFIG_MRC_TX
int valid_mrc_mask;
#endif // CONFIG_MRC_TX
// Only for INTRA blocks
UV_PREDICTION_MODE uv_mode;
......@@ -716,10 +712,6 @@ typedef struct macroblockd {
DECLARE_ALIGNED(16, uint8_t, seg_mask[2 * MAX_SB_SQUARE]);
#if CONFIG_MRC_TX
uint8_t *mrc_mask;
#endif // CONFIG_MRC_TX
#if CONFIG_CFL
CFL_CTX *cfl;
#endif
......@@ -765,23 +757,11 @@ static INLINE int block_signals_txsize(BLOCK_SIZE bsize) {
return bsize > BLOCK_4X4;
}
#if CONFIG_MRC_TX
#define USE_MRC_INTRA 0
#define USE_MRC_INTER 1
#define SIGNAL_MRC_MASK_INTRA (USE_MRC_INTRA && 0)
#define SIGNAL_MRC_MASK_INTER (USE_MRC_INTER && 1)
#define SIGNAL_ANY_MRC_MASK (SIGNAL_MRC_MASK_INTRA || SIGNAL_MRC_MASK_INTER)
#endif // CONFIG_MRC_TX
#define ALLOW_INTRA_EXT_TX 1
// Number of transform types in each set type
static const int av1_num_ext_tx_set[EXT_TX_SET_TYPES] = {
1, 2,
#if CONFIG_MRC_TX
2, 3,
#endif // CONFIG_MRC_TX
5, 7, 12, 16,
1, 2, 5, 7, 12, 16,
};
static const int av1_ext_tx_set_idx_to_type[2][AOMMAX(EXT_TX_SETS_INTRA,
......@@ -789,48 +769,14 @@ static const int av1_ext_tx_set_idx_to_type[2][AOMMAX(EXT_TX_SETS_INTRA,
{
// Intra
EXT_TX_SET_DCTONLY, EXT_TX_SET_DTT4_IDTX_1DDCT, EXT_TX_SET_DTT4_IDTX,
#if CONFIG_MRC_TX
EXT_TX_SET_MRC_DCT,
#endif // CONFIG_MRC_TX
},
{
// Inter
EXT_TX_SET_DCTONLY, EXT_TX_SET_ALL16, EXT_TX_SET_DTT9_IDTX_1DDCT,
EXT_TX_SET_DCT_IDTX,
#if CONFIG_MRC_TX
EXT_TX_SET_MRC_DCT_IDTX,
#endif // CONFIG_MRC_TX
}
};
#if CONFIG_MRC_TX
static const int av1_ext_tx_used[EXT_TX_SET_TYPES][TX_TYPES] = {
{
1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
},
{
1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0,
},
{
1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1,
},
{
1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1,
},
{
1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0,
},
{
1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0,
},
{
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
},
{
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0,
},
};
#else // CONFIG_MRC_TX
static const int av1_ext_tx_used[EXT_TX_SET_TYPES][TX_TYPES] = {
{
1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
......@@ -851,7 +797,6 @@ static const int av1_ext_tx_used[EXT_TX_SET_TYPES][TX_TYPES] = {
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
},
};
#endif // CONFIG_MRC_TX
static INLINE TxSetType get_ext_tx_set_type(TX_SIZE tx_size, BLOCK_SIZE bs,
int is_inter, int use_reduced_set) {
......@@ -865,14 +810,6 @@ static INLINE TxSetType get_ext_tx_set_type(TX_SIZE tx_size, BLOCK_SIZE bs,
#endif // USE_TXTYPE_SEARCH_FOR_SUB8X8_IN_CB4X4
if (use_reduced_set)
return is_inter ? EXT_TX_SET_DCT_IDTX : EXT_TX_SET_DTT4_IDTX;
#if CONFIG_MRC_TX
if (tx_size == TX_32X32) {
if (is_inter && USE_MRC_INTER)
return EXT_TX_SET_MRC_DCT_IDTX;
else if (!is_inter && USE_MRC_INTRA)
return EXT_TX_SET_MRC_DCT;
}
#endif // CONFIG_MRC_TX
#if CONFIG_DAALA_TX32
if (tx_size_sqr_up > TX_32X32)
return is_inter ? EXT_TX_SET_DCT_IDTX : EXT_TX_SET_DCTONLY;
......@@ -897,19 +834,11 @@ static INLINE TxSetType get_ext_tx_set_type(TX_SIZE tx_size, BLOCK_SIZE bs,
static const int ext_tx_set_index[2][EXT_TX_SET_TYPES] = {
{
// Intra
0, -1,
#if CONFIG_MRC_TX
3, -1,
#endif // CONFIG_MRC_TX
2, 1, -1, -1,
0, -1, 2, 1, -1, -1,
},
{
// Inter
0, 3,
#if CONFIG_MRC_TX
-1, 4,
#endif // CONFIG_MRC_TX
-1, -1, 2, 1,
0, 3, -1, -1, 2, 1,
},
};
......@@ -1089,18 +1018,6 @@ static INLINE TX_TYPE av1_get_tx_type(PLANE_TYPE plane_type,
return get_default_tx_type(plane_type, xd, block_raster_idx, tx_size);
#endif // FIXED_TX_TYPE
#if CONFIG_MRC_TX
if (mbmi->tx_type == MRC_DCT) {
assert(((is_inter_block(mbmi) && USE_MRC_INTER) ||
(!is_inter_block(mbmi) && USE_MRC_INTRA)) &&
"INVALID BLOCK TYPE FOR MRC_DCT");
if (plane_type == PLANE_TYPE_Y) {
assert(tx_size == TX_32X32);
return mbmi->tx_type;
}
return DCT_DCT;
}
#endif // CONFIG_MRC_TX
#if CONFIG_DAALA_TX32
if (xd->lossless[mbmi->segment_id] || txsize_sqr_map[tx_size] > TX_32X32)
#else
......
......@@ -1738,9 +1738,6 @@ void av1_average_tile_intra_cdfs(FRAME_CONTEXT *fc, FRAME_CONTEXT *ec_ctxs[],
AVERAGE_TILE_CDFS(filter_intra_cdfs)
AVERAGE_TILE_CDFS(filter_intra_mode_cdf)
#endif
#if CONFIG_MRC_TX
AVERAGE_TILE_CDFS(mrc_mask_intra_cdf)
#endif // CONFIG_MRC_TX
AVERAGE_TILE_CDFS(palette_y_mode_cdf)
AVERAGE_TILE_CDFS(palette_uv_mode_cdf)
#if CONFIG_EXT_INTRA_MOD
......@@ -1802,9 +1799,6 @@ void av1_average_tile_inter_cdfs(AV1_COMMON *cm, FRAME_CONTEXT *fc,
AVERAGE_TILE_CDFS(intra_inter_cdf)
AVERAGE_TILE_CDFS(motion_mode_cdf)
AVERAGE_TILE_CDFS(obmc_cdf)
#if CONFIG_MRC_TX
AVERAGE_TILE_CDFS(mrc_mask_inter_cdf)
#endif // CONFIG_MRC_TX
#if CONFIG_LPF_SB
AVERAGE_TILE_CDFS(lpf_reuse_cdf);
AVERAGE_TILE_CDFS(lpf_delta_cdf);
......
......@@ -1186,114 +1186,6 @@ const aom_cdf_prob default_palette_uv_color_index_cdf
{ AOM_CDF8(30208, 30628, 31046, 31658, 31762, 32367, 32469) },
}
};
#if CONFIG_MRC_TX
// TODO(sarahparker) Tune these cdfs
const aom_cdf_prob default_mrc_mask_intra_cdf
[PALETTE_SIZES][PALETTE_COLOR_INDEX_CONTEXTS][CDF_SIZE(PALETTE_COLORS)] = {
{
{ AOM_CDF2(29568), 0, 0, 0, 0, 0, 0 },
{ AOM_CDF2(16384), 0, 0, 0, 0, 0, 0 },
{ AOM_CDF2(8832), 0, 0, 0, 0, 0, 0 },
{ AOM_CDF2(28672), 0, 0, 0, 0, 0, 0 },
{ AOM_CDF2(31872), 0, 0, 0, 0, 0, 0 },
},
{
{ AOM_CDF3(28032, 30326), 0, 0, 0, 0, 0 },
{ AOM_CDF3(11647, 27405), 0, 0, 0, 0, 0 },
{ AOM_CDF3(4352, 30659), 0, 0, 0, 0, 0 },
{ AOM_CDF3(23552, 27800), 0, 0, 0, 0, 0 },
{ AOM_CDF3(32256, 32504), 0, 0, 0, 0, 0 },
},
{
{ AOM_CDF4(26112, 28374, 30039), 0, 0, 0, 0 },
{ AOM_CDF4(9472, 22576, 27712), 0, 0, 0, 0 },
{ AOM_CDF4(6656, 26138, 29608), 0, 0, 0, 0 },
{ AOM_CDF4(19328, 23791, 28946), 0, 0, 0, 0 },
{ AOM_CDF4(31744, 31984, 32336), 0, 0, 0, 0 },
},
{
{ AOM_CDF5(27904, 29215, 30075, 31190), 0, 0, 0 },
{ AOM_CDF5(9728, 22598, 26134, 29425), 0, 0, 0 },
{ AOM_CDF5(2688, 30066, 31058, 31933), 0, 0, 0 },
{ AOM_CDF5(22015, 25039, 27726, 29932), 0, 0, 0 },
{ AOM_CDF5(32383, 32482, 32554, 32660), 0, 0, 0 },
},
{
{ AOM_CDF6(24319, 26299, 27486, 28600, 29804), 0, 0 },
{ AOM_CDF6(7935, 18217, 21116, 25440, 28589), 0, 0 },
{ AOM_CDF6(6656, 25016, 27105, 28698, 30399), 0, 0 },
{ AOM_CDF6(19967, 24117, 26550, 28566, 30224), 0, 0 },
{ AOM_CDF6(31359, 31607, 31775, 31977, 32258), 0, 0 },
},
{
{ AOM_CDF7(26368, 27768, 28588, 29274, 29997, 30917), 0 },
{ AOM_CDF7(8960, 18260, 20810, 23986, 26627, 28882), 0 },
{ AOM_CDF7(7295, 24111, 25836, 27515, 29033, 30769), 0 },
{ AOM_CDF7(22016, 25208, 27305, 28159, 29221, 30274), 0 },
{ AOM_CDF7(31744, 31932, 32050, 32199, 32335, 32521), 0 },
},
{
{ AOM_CDF8(26624, 27872, 28599, 29153, 29633, 30172, 30841) },
{ AOM_CDF8(6655, 17569, 19587, 23345, 25884, 28088, 29678) },
{ AOM_CDF8(3584, 27296, 28429, 29158, 30032, 30780, 31572) },
{ AOM_CDF8(23551, 25855, 27070, 27893, 28597, 29721, 30970) },
{ AOM_CDF8(32128, 32173, 32245, 32337, 32416, 32500, 32609) },
},
};
const aom_cdf_prob default_mrc_mask_inter_cdf
[PALETTE_SIZES][PALETTE_COLOR_INDEX_CONTEXTS][CDF_SIZE(PALETTE_COLORS)] = {
{
{ AOM_CDF2(29568), 0, 0, 0, 0, 0, 0 },
{ AOM_CDF2(16384), 0, 0, 0, 0, 0, 0 },
{ AOM_CDF2(8832), 0, 0, 0, 0, 0, 0 },
{ AOM_CDF2(28672), 0, 0, 0, 0, 0, 0 },
{ AOM_CDF2(31872), 0, 0, 0, 0, 0, 0 },
},
{
{ AOM_CDF3(28032, 30326), 0, 0, 0, 0, 0 },
{ AOM_CDF3(11647, 27405), 0, 0, 0, 0, 0 },
{ AOM_CDF3(4352, 30659), 0, 0, 0, 0, 0 },
{ AOM_CDF3(23552, 27800), 0, 0, 0, 0, 0 },
{ AOM_CDF3(32256, 32504), 0, 0, 0, 0, 0 },
},
{
{ AOM_CDF4(26112, 28374, 30039), 0, 0, 0, 0 },
{ AOM_CDF4(9472, 22576, 27712), 0, 0, 0, 0 },
{ AOM_CDF4(6656, 26138, 29608), 0, 0, 0, 0 },
{ AOM_CDF4(19328, 23791, 28946), 0, 0, 0, 0 },
{ AOM_CDF4(31744, 31984, 32336), 0, 0, 0, 0 },
},
{
{ AOM_CDF5(27904, 29215, 30075, 31190), 0, 0, 0 },
{ AOM_CDF5(9728, 22598, 26134, 29425), 0, 0, 0 },
{ AOM_CDF5(2688, 30066, 31058, 31933), 0, 0, 0 },
{ AOM_CDF5(22015, 25039, 27726, 29932), 0, 0, 0 },
{ AOM_CDF5(32383, 32482, 32554, 32660), 0, 0, 0 },
},
{
{ AOM_CDF6(24319, 26299, 27486, 28600, 29804), 0, 0 },
{ AOM_CDF6(7935, 18217, 21116, 25440, 28589), 0, 0 },
{ AOM_CDF6(6656, 25016, 27105, 28698, 30399), 0, 0 },
{ AOM_CDF6(19967, 24117, 26550, 28566, 30224), 0, 0 },
{ AOM_CDF6(31359, 31607, 31775, 31977, 32258), 0, 0 },
},
{
{ AOM_CDF7(26368, 27768, 28588, 29274, 29997, 30917), 0 },
{ AOM_CDF7(8960, 18260, 20810, 23986, 26627, 28882), 0 },
{ AOM_CDF7(7295, 24111, 25836, 27515, 29033, 30769), 0 },
{ AOM_CDF7(22016, 25208, 27305, 28159, 29221, 30274), 0 },
{ AOM_CDF7(31744, 31932, 32050, 32199, 32335, 32521), 0 },
},
{
{ AOM_CDF8(26624, 27872, 28599, 29153, 29633, 30172, 30841) },
{ AOM_CDF8(6655, 17569, 19587, 23345, 25884, 28088, 29678) },
{ AOM_CDF8(3584, 27296, 28429, 29158, 30032, 30780, 31572) },
{ AOM_CDF8(23551, 25855, 27070, 27893, 28597, 29721, 30970) },
{ AOM_CDF8(32128, 32173, 32245, 32337, 32416, 32500, 32609) },
},
};
#endif // CONFIG_MRC_TX
#if CONFIG_INTRABC
static const aom_cdf_prob default_intrabc_cdf[CDF_SIZE(2)] = { AOM_CDF2(192 *
......@@ -1912,70 +1804,6 @@ static const aom_cdf_prob default_intra_ext_tx_cdf
{ AOM_CDF5(1280, 5216, 6938, 13396) },
},
},
#if CONFIG_MRC_TX
{
{
{ AOM_CDF2(1024) },
{ AOM_CDF2(1280) },