From 492fc927268752da4cae855652b34cbaa93ebe44 Mon Sep 17 00:00:00 2001
From: Ray Essick <essick@google.com>
Date: Thu, 24 Aug 2017 05:32:42 -0700
Subject: [PATCH] fix alignment exceptions

some SSE optimizations were using an instruction sequence that required
128-bit alignment, even though this is not always guaranteed. The error
was in handling a 64-bit entity; made the same macro changes that had
been done previously for 32-bit entities.

Signed-off-by: Felicia Lim <flim@google.com>
---
 celt/x86/x86cpu.h | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/celt/x86/x86cpu.h b/celt/x86/x86cpu.h
index 04fd48aac..1e2bf17b9 100644
--- a/celt/x86/x86cpu.h
+++ b/celt/x86/x86cpu.h
@@ -82,7 +82,9 @@ int opus_select_arch(void);
  (_mm_cvtepi8_epi32(*(__m128i *)(x)))
 #endif
 
-# if !defined(__OPTIMIZE__)
+/* similar reasoning about the instruction sequence as in the 32-bit macro above,
+ */
+# if defined(__clang__) || !defined(__OPTIMIZE__)
 #  define OP_CVTEPI16_EPI32_M64(x) \
  (_mm_cvtepi16_epi32(_mm_loadl_epi64((__m128i *)(x))))
 # else
-- 
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