Fix the VS build failure.

Change-Id: I4fb9d1c83980c4b52d5a848a9cb02ec72493dccb

Change-Id: If536ad31046ecd9e2ecd9c21f52f8192c8153ad7

Change-Id: Ie8a79d9e2837842c3f60776b661cd42782b108d5

This commit moves the module inverse transform functions from vp9
to vpx_dsp folder. The hybrid transform wrapper functions stay in
the vp9 folder, since it involves codec-specific data structures.

Change-Id: Ib066367c953d3d024c73ba65157bbd70a95c9ef8

This got erroneously changed during the refactor. This fixes
SvcTest.TwoPassEncode2TemporalLayersWithMultipleFrameContextsAndTiles.

Change-Id: Ifa5ab0e098396c5e2d10478db87df256eadfa4c7

* changes:
  Android.mk: fix *_rtcd.h deps for armeabi-v7a
  Android.mk: add a dep on vpx_config.asm for x86_64

This function suffers from a couple problems in small core(tablets):
-The load of the next iteration is blocked by the store of previous iteration
-4k aliasing (between future store and older loads)
-current small core machine are in-order machine and because of it the store will spin the rehabQ until the load is finished
fixed by:
- prefetching 2 lines ahead
- unroll copy of 2 rows of block
- pre-load all xmm regiters before the loop, final stores after the loop
The function is optimized by:
copy_convolve_sse2 64x64 - 16%
copy_convolve_sse2 32x32 - 52%
copy_convolve_sse2 16x16 - 6%
copy_convolve_sse2 8x8 - 2.5%
copy_convolve_sse2 4x4 - 2.7%
credit goes to Tom Craver(tom.r.craver@intel.com) and Ilya Albrekht(ilya.albrekht@intel.com)

Change-Id: I63d3428799c50b2bf7b5677c8268bacb9fc29671

This commit fixes the mix declaration and definition warning when
mips/dspr2 is turned on.

Change-Id: I633d6fe42368b9ac35b106786ebac6969ad53552

* changes:
  Simplify model_rd_for_sb HBD ifdefs
  Simplify dist_block HBD ifdefs

Change-Id: Iaa43aeeb7a2074495e00cdb83bb551c3f13d3ed2

Change-Id: Ic1ce346a053800ae3b2d77178f46e6a388357f6d

Change-Id: Ic0b4e92cbaf813bcca8a8e9052c936c2e025e114

Change-Id: If59a39d5a92c261537342726f94bb7f7f26dfff3

It in essence refactors the code for both the interpolation
filtering and the convolution. This change includes the moving
of all the files as well as the changing of the code from vp9_
prefix to vpx_ prefix accordingly, for underneath architectures:
(1) x86;
(2) arm/neon; and
(3) mips/msa.
The work on mips/drsp2 will be done in a separate change list.

Change-Id: Ic3ce7fb7f81210db7628b373c73553db68793c46

This is using a define instead of an enum to keep byte packing.

Change-Id: I3abb07c8bfe377e19be4531b624af7b7b4207792

Don't run rate_block (cost_coeffs) if distortion alone is enough to
surpass best_rd.

This decreases 2nd pass runtime on HD at speed 2 by about 2%. There is
zero effect on output if tx_cache is removed.

Change-Id: Ia3b1cc77bfbe6ee988c395fde06c0eb92940b784

average improvement ~2x-3x

Change-Id: I05593bed583234dc7809aaec6cab82773a29505d

average improvement ~2x-3x

Change-Id: I30abf4c92cddcc9e87b7a40d4106076e1ec701c2

1. The RD scores obtained during the tx size selection were stored in the
tx cache, and used to help make the tx decision for the following frames.
This wasn't used anymore in VP9 encoder. Recovered the related decision
making code from 1.5+ years ago, and borg tests didn't show any quality
gain. This patch removed it to lower the complexity.

2. An optimization was done after the above refactoring. If the tx_mode
is not TX_MODE_SELECT, we only need to test the chosen tx size instead
of all posible tx sizes. This gave a 1.5% average speed gain at speed 2,
and a 1% average speed gain at speed 3.

Change-Id: Id8cd650e066a8cef33829d8c15388a8138adc78c

Change-Id: I8877025e172fff29bc4e270790211463b676b4d7

Currently vp8 is not using the intra prediction functions in vpx_dsp.

Change-Id: I1522b5f5cb12a81999fb126cf7c62c70259e7a52

strip '.neon' so *_rtcd.h depends on the correct file

Change-Id: Iecdbbc34c9ce5c6d0a4b466332d52f4e6a0cb128

Parag Salasakar authored 9 years ago and James Zern committed 9 years ago

average improvement ~2x-3x

Change-Id: I6fc37191bf9cb5a67e1af9787d0d27659c17bdba

Change-Id: I9d613cbe9e76b5dd15e935878ef9fd04521690ba