- Jul 06, 2016
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Signed-off-by:
Timothy B. Terriberry <tterribe@xiph.org>
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Signed-off-by:
Timothy B. Terriberry <tterribe@xiph.org>
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Signed-off-by:
Timothy B. Terriberry <tterribe@xiph.org>
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Used for celt_pitch_xcorr on aarch64, and celt_fir and celt_iir on both armv7 and aarch64. Signed-off-by:
Timothy B. Terriberry <tterribe@xiph.org>
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Signed-off-by:
Timothy B. Terriberry <tterribe@xiph.org>
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Signed-off-by:
Timothy B. Terriberry <tterribe@xiph.org>
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Signed-off-by:
Timothy B. Terriberry <tterribe@xiph.org>
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Mark Harris authored
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- Jun 20, 2016
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Jean-Marc Valin authored
Reported by Durandal.
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- Jun 18, 2016
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Jean-Marc Valin authored
This could lead to an integer overflow. Also, refactored the code a bit
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Jean-Marc Valin authored
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- Apr 16, 2016
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Avoids generating comfort noise with unwanted tones in DTX mode.
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- Mar 24, 2016
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Jean-Marc Valin authored
As reported by Giovanni Rovatti, this should fix some TI C55 issues.
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- Dec 31, 2015
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Jean-Marc Valin authored
Avoids accidental name collisions
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- Dec 23, 2015
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Jean-Marc Valin authored
...and also make it not ignore the right channel
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Jean-Marc Valin authored
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- Dec 04, 2015
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Jean-Marc Valin authored
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Jean-Marc Valin authored
Reported in https://trac.xiph.org/ticket/2241
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Jean-Marc Valin authored
Should no longer cause discontinuities in the noise after 5 packets
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Jean-Marc Valin authored
Previously silence would cause the divide approximation on 0/0 to return a very large value, which would be interpreted as a transient
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- Nov 23, 2015
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Signed-off-by:
Jean-Marc Valin <jmvalin@jmvalin.ca>
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- Nov 05, 2015
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Signed-off-by:
Timothy B. Terriberry <tterribe@xiph.org>
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Signed-off-by:
Timothy B. Terriberry <tterribe@xiph.org>
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- Nov 03, 2015
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- Oct 08, 2015
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Signed-off-by:
Jean-Marc Valin <jmvalin@jmvalin.ca>
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- Oct 07, 2015
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Some of the fields present in NE10's float state struct are not present in the fixed-point version, but we were generating initializers for them anyway. Also, the float modes were not up-to-date with the output of dump_modes.
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Extends usage of NEON optimized fixed-point FFT optimizations in libNE10 to clt_mdct_forward and clt_mdct_backward. Signed-off-by:
Timothy B. Terriberry <tterribe@xiph.org>
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Uses NEON optimized fixed point FFT routines in NE10 library. Signed-off-by:
Timothy B. Terriberry <tterribe@xiph.org>
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Signed-off-by:
Viswanath Puttagunta <viswanath.puttagunta@linaro.org> Signed-off-by:
Timothy B. Terriberry <tterribe@xiph.org>
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Optimize opus decode (float only) use case using ARM NE10. Mainly effects opus_ifft and ctl_mdct_backward and related functions. Work based on previous Encode optimization using ARM NE10 library. See previous commit for details on how to enable this. Signed-off-by:
Timothy B. Terriberry <tterribe@xiph.org>
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Optimize opus encode (float only) usecase using ARM NE10 library. Mainly effects opus_fft and ctl_mdct_forward and related functions. This optimization can be used for ARM CPUs that have NEON VFP unit. This patch only enables optimizations for ARMv7. Official ARM NE10 library page available at http://projectne10.github.io/Ne10/ To enable this optimization, use --enable-intrinsics --with-NE10=<install_prefix> or --enable-intrinsics --with-NE10-libraries=<NE10_lib_dir> --with-NE10-includes=<NE10_includes_dir> Compile time checks made during configure process to make sure optimization option available only when compiler supports NEON instrinsics. Runtime checks made to make sure optimized functions only called on appropriate hardware. Signed-off-by:
Timothy B. Terriberry <tterribe@xiph.org>
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This is needed for the SMALL_DIV_TABLE constants added in commit ec5d01cb.
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Brings MIPS in sync with the ARM/SSE optimizations that added "arch" parameters. Signed-off-by:
Jean-Marc Valin <jmvalin@jmvalin.ca>
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- Sep 01, 2015
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Enable x86 intrinsics when building in floating-point mode. Support SSE as an arch value. Use RTCD to conditionally enable existing floating-point Celt SSE code. Call functions directly (without RTCD) when their architecture can be presumed. Use SSE4.1 intrinsics optimized code for Silk even in floating-point mode.
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Move SSE2 and SSE4.1 intrinsics functions to separate files, to be compiled with appropriate compiler flags. Otherwise, compilers are allowed to take advantage of (e.g.) -msse4.1 to generate code that uses SSE4.1 instructions, even when no SSE4.1 intrinsics are explicitly used in the source.
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