Rename, reindent, change arg order

Jean-Marc Valin authored 1 year ago and Jean-Marc Valin committed 1 year ago

Need to move the redundant frame even in CBR because the hybrid
frame now gets encoded as VBR, with DRED picking up the rest.
Fixes an issue introduced in 4600e775.

Jean-Marc Valin authored 1 year ago and Jean-Marc Valin committed 1 year ago

The encoder wouldn't reserve enough bits for CELT, causing it
to not have enough bits to code the switching redundancy flag
when it should have.

Adjust q0, qD and duration based on bitrate and loss.

No longer needed now that PLC is trained with PyTorch stack

Should handle the history in a more consistent way.
Slightly increase the model size and re-enable biased band loss in
training.

mostly untested

Should match the TF2 code, but mostly untested

Constrains the energy prediction to something safe.

Avoids valgrind complaining about use of uninitialized memory