No longer needed now that PLC is trained with PyTorch stack

Should handle the history in a more consistent way.
Slightly increase the model size and re-enable biased band loss in
training.

mostly untested

Should match the TF2 code, but mostly untested

Constrains the energy prediction to something safe.

Avoids valgrind complaining about use of uninitialized memory

Removes float debug weights, as well as useless spaces

Use OPUS_DRED instead of NEURAL_FEC

Also default to disabling dnn float debugging

Still don't quite know what I'm doing

Compilers sometimes replace vmlaq*() with fmul+fadd instead of fmla.
Trying to use vfmaq*() instead when possible.

Finished adversarial training on 800k model. Also, move weights to a new
location.

1) Enable asm/intrinsics even for floating-point
2) Make sure ARMv8 asimd enables EDSP/MEDIA/Neon
3) Add dotp architecture to rtcd table since AArch *can* have dotp

Adds RTCD tables for compute_activation() and compute_conv2d()

Avoids having to write intrinsics for simple loops