- Jul 27, 2023
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Jean-Marc Valin authored
And missing prototypes
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Jean-Marc Valin authored
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Jean-Marc Valin authored
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- Jul 24, 2023
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Jan Buethe authored
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- Jul 23, 2023
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Jean-Marc Valin authored
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Jean-Marc Valin authored
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Jean-Marc Valin authored
Untested
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- Jul 22, 2023
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Jan Buethe authored
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Jan Buethe authored
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Jan Buethe authored
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Jan Buethe authored
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Jan Buethe authored
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Jan Buethe authored
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Jan Buethe authored
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Jan Buethe authored
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Jan Buethe authored
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Jean-Marc Valin authored
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Jean-Marc Valin authored
Not so much for old machines, as for getting decent performance when not setting -march= (SSE2 is part of the amd64 ABI).
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Jean-Marc Valin authored
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Jan Buethe authored
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- Jul 20, 2023
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Jean-Marc Valin authored
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Jean-Marc Valin authored
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Jean-Marc Valin authored
Should be able to handle all previous GRU variants and more.
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Jean-Marc Valin authored
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- Jul 12, 2023
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Jean-Marc Valin authored
Should work for both CBR and VBR. In the CBR case, we can make CELT VBR and use DRED to fill the rest.
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Jean-Marc Valin authored
If configuring CELT for CBR but controlling the bitrate with OPUS_SET_BITRATE rather than nbCompressedBytes, then the range coder buffer would never get resized. AFAICT this could never be triggered in Opus because CBR was also controlled by nbCompressedBytes.
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Jean-Marc Valin authored
CELT encoding would just fail when setting CELT to CBR in hybrid mode. It was never a problem because hybrid CBR was always used with OPUS_BITRATE_MAX.
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Jean-Marc Valin authored
Avoids interactions with redundancy settings
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Jean-Marc Valin authored
SET_BITRATE is now the total bitrate again
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Jean-Marc Valin authored
We weren't reserving enough bytes for the DRED extension
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Jean-Marc Valin authored
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Jean-Marc Valin authored
The bits we don't use won't be wasted, so it's less important to get exactly the optimal number of bits below the cap.
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Jean-Marc Valin authored
The gain*2 when overshooting was too aggressive and the undershoot case wasn't aggressive enough. This now seems to work reasonably well.
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Jean-Marc Valin authored
Don't attempt to run the neural PLC on the side channel since we only have one state.
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- Jul 03, 2023
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Jean-Marc Valin authored
Also, don't code DRED that's redundant with the main packet
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- Jul 01, 2023
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Michael Klingbeil authored
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- Jun 30, 2023
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- Jun 28, 2023
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Jean-Marc Valin authored
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Jean-Marc Valin authored
Should make synthesis easier in the future
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- Jun 27, 2023
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Jean-Marc Valin authored
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