1) Enable asm/intrinsics even for floating-point
2) Make sure ARMv8 asimd enables EDSP/MEDIA/Neon
3) Add dotp architecture to rtcd table since AArch *can* have dotp

Not yet with rtcd

Fixes warnings, undefined behaviour, and check-asm failure

Victor Ding authored 1 year ago and Jean-Marc Valin committed 1 year ago

The optimization is bit-exact with C function.

This optimization speeds up SILK encoder (floating point) as following:

AMD Zen:
Complexity 0-5 :      0%
Complexity 6-7 : 3 -  7%
Complexity 8-10: 8 - 15%

Intel Skylake:
Complexity 0-5 :       0%
Complexity 6-7 : 14 - 18%
Complexity 8-10: 17 - 22%

Adapted by Jean-Marc Valin

Not hooked up

Reducing the dependency chain between tmp1 and tmp2 at the
cost of an extra multiply.

Starting with compute_linear()

Saves ~270 kB of weights in the decoder

Removing some indirections

Only code non-degenerate symbols, which makes the encoder faster

Felicia Lim authored 1 year ago and Jean-Marc Valin committed 1 year ago

Update silk/x86/NSQ_del_dec_sse4_1.c to match the remaining
silk/NSQ_del_dec.c changes made in
c913dc38



Signed-off-by: Jean-Marc Valin <jmvalin@jmvalin.ca>

Felicia Lim authored 1 year ago and Jean-Marc Valin committed 1 year ago

Co-authored-by: James Zern <jzern@google.com>

Controls whether deep PLC is enabled

No dependency on the data files if no DNN code enabled

Signed-off-by: Jean-Marc Valin <jmvalin@amazon.com>

Signed-off-by: Jean-Marc Valin <jmvalin@amazon.com>

Those intrinsics don't actually require alignment so we're OK

Using a max lambda of 0.04

Remove old pitch estimator and retrain all models

More efficient than PVQ

There was a suggestion to use 127 for extending the extension ID space

When ready, change DRED_EXTENSION_ID to the final ID, remove
DRED_EXPERIMENTAL_VERSION completely, and change DRED_EXPERIMENTAL_BYTES
to zero (eventually remove it).