Felicia Lim authored 1 year ago and Jean-Marc Valin committed 1 year ago

Update silk/x86/NSQ_del_dec_sse4_1.c to match the remaining
silk/NSQ_del_dec.c changes made in
c913dc38



Signed-off-by: Jean-Marc Valin <jmvalin@jmvalin.ca>

Felicia Lim authored 1 year ago and Jean-Marc Valin committed 1 year ago

Co-authored-by: James Zern <jzern@google.com>

Controls whether deep PLC is enabled

No dependency on the data files if no DNN code enabled

Signed-off-by: Jean-Marc Valin <jmvalin@amazon.com>

Signed-off-by: Jean-Marc Valin <jmvalin@amazon.com>

Those intrinsics don't actually require alignment so we're OK

Using a max lambda of 0.04

Remove old pitch estimator and retrain all models

More efficient than PVQ

There was a suggestion to use 127 for extending the extension ID space

When ready, change DRED_EXTENSION_ID to the final ID, remove
DRED_EXPERIMENTAL_VERSION completely, and change DRED_EXPERIMENTAL_BYTES
to zero (eventually remove it).

The bits we don't use won't be wasted, so it's less important to
get exactly the optimal number of bits below the cap.

The gain*2 when overshooting was too aggressive and the undershoot
case wasn't aggressive enough. This now seems to work reasonably well.

Don't attempt to run the neural PLC on the side channel since
we only have one state.

Also, don't code DRED that's redundant with the main packet

Should make synthesis easier in the future

8k, 12k and stereo are mostly untested